UPD78F9502MA-CAC-A NEC, UPD78F9502MA-CAC-A Datasheet - Page 115
UPD78F9502MA-CAC-A
Manufacturer Part Number
UPD78F9502MA-CAC-A
Description
8BIT MCU, 4K FLASH, 128B RAM, SMD
Manufacturer
NEC
Datasheet
1.UPD78F9502MA-CAC-A.pdf
(229 pages)
Specifications of UPD78F9502MA-CAC-A
Controller Family/series
UPD78F
No. Of I/o's
8
Ram Memory Size
128Byte
Cpu Speed
10MHz
No. Of Timers
2
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
4KB
Oscillator Type
External, Internal
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Reset signal of POC
High-speed internal oscillation clock or
Reset signal of LVI
Caution The LVI circuit is not reset by the internal reset signal of the LVI circuit.
Remarks 1. LVIM: Low-voltage detect register
Note
RESET
Reset signal of WDT
The operation stop time is 277 s (MIN.), 544 s (TYP.), and 1.075 ms (MAX.).
2. LVIS: Low-voltage detection level select register
Internal reset signal
external clock input
CPU clock
Port pin
RESET
Figure 10-1. Block Diagram of Reset Function
Figure 10-2. Timing of Reset by RESET Input
Normal operation
Set
WDTRF
Clear
in progress
Preliminary User’s Manual U18681EJ1V0UD
CHAPTER 10 RESET FUNCTION
LVIRF
Set
100 ns (TYP.)
Reset control flag register (RESF)
Internal bus
Delay
Clear
(oscillation stops)
Reset period
100 ns (TYP.)
Delay
Operation stops because option
byte is referenced
Normal operation (reset processing, CPU clock)
Hi-Z
Reset signal to LVIM/LVIS register
Internal reset signal
Note 1
.
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