UPD78F9502MA-CAC-A NEC, UPD78F9502MA-CAC-A Datasheet - Page 116
UPD78F9502MA-CAC-A
Manufacturer Part Number
UPD78F9502MA-CAC-A
Description
8BIT MCU, 4K FLASH, 128B RAM, SMD
Manufacturer
NEC
Datasheet
1.UPD78F9502MA-CAC-A.pdf
(229 pages)
Specifications of UPD78F9502MA-CAC-A
Controller Family/series
UPD78F
No. Of I/o's
8
Ram Memory Size
128Byte
Cpu Speed
10MHz
No. Of Timers
2
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
4KB
Oscillator Type
External, Internal
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High-speed internal oscillation clock or
High-speed internal oscillation clock or
Note
Caution The watchdog timer is also reset in the case of an internal reset of the watchdog timer.
Note
Remark
The operation stop time is 277 s (MIN.), 544 s (TYP.), and 1.075 ms (MAX.).
The operation stop time is 277 s (MIN.), 544 s (TYP.), and 1.075 ms (MAX.).
Internal reset signal
Internal reset signal
external clock input
external clock input
Watchdog overflow
For the reset timing of the power-on-clear circuit and low-voltage detector, refer to CHAPTER 11
POWER-ON-CLEAR CIRCUIT and CHAPTER 12 LOW-VOLTAGE DETECTOR.
CPU clock
CPU clock
Port pin
RESET
Port pin
Figure 10-3. Timing of Reset by Overflow of Watchdog Timer
Figure 10-4. Reset Timing by RESET Input in STOP Mode
in progress
operation
Normal operation
STOP instruction is executed.
Normal
in progress
Preliminary User’s Manual U18681EJ1V0UD
CHAPTER 10 RESET FUNCTION
(oscillation stops)
Stop status
100 ns (TYP.)
Delay
(oscillation stops)
(oscillation stops)
Reset period
Reset period
100 ns (TYP.)
Delay
Operation stops because option
byte is referenced
Operation stops because option
byte is referenced
Normal operation (reset processing, CPU clock)
Normal operation (reset processing, CPU clock)
Hi-Z
Hi-Z
Note 1
Note
.
.
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