UPD78F9502MA-CAC-A NEC, UPD78F9502MA-CAC-A Datasheet - Page 150
UPD78F9502MA-CAC-A
Manufacturer Part Number
UPD78F9502MA-CAC-A
Description
8BIT MCU, 4K FLASH, 128B RAM, SMD
Manufacturer
NEC
Datasheet
1.UPD78F9502MA-CAC-A.pdf
(229 pages)
Specifications of UPD78F9502MA-CAC-A
Controller Family/series
UPD78F
No. Of I/o's
8
Ram Memory Size
128Byte
Cpu Speed
10MHz
No. Of Timers
2
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
4KB
Oscillator Type
External, Internal
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2. Operating conditions of VCERR flag
3. Operating conditions of WEPRERR flag
<Reset conditions>
<Setting conditions>
<Reset conditions>
<Setting conditions>
<Reset conditions>
If a value other than the inverted value of the value to be set to FLPMC is written by the first store instruction
after <2>
If the first store instruction operation after <3> is on a peripheral register other than FLPMC
If a value other than the value to be set to FLPMC (value written in <2>) is written by the first store instruction
after <3>
Remark The numbers in angle brackets above correspond to the those in (2) Flash protect command
If 0 is written to the FPRERR flag
If the reset signal is generation
Erasure verification error
Internal writing verification error
If VCERR is set, it means that the flash memory has not been erased or written correctly. Erase or write the
memory again in the specified procedure.
Remark The VCERR flag may also be set if an erase or write protect error occurs.
When 0 is written to the VCERR flag
When the reset signal generation
If the area specified by the protect byte to be protected from erasing or writing is specified by the flash
address pointer H (FLAPH) and a command is executed to this area
If 1 is written to a bit that has not been erased (a bit for which the data is 0).
When 0 is written to the WEPRERR flag
When the reset signal generation
register (PFCMD).
Preliminary User’s Manual U18681EJ1V0UD
CHAPTER 14 FLASH MEMORY
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