UPD78F9502MA-CAC-A NEC, UPD78F9502MA-CAC-A Datasheet - Page 68
UPD78F9502MA-CAC-A
Manufacturer Part Number
UPD78F9502MA-CAC-A
Description
8BIT MCU, 4K FLASH, 128B RAM, SMD
Manufacturer
NEC
Datasheet
1.UPD78F9502MA-CAC-A.pdf
(229 pages)
Specifications of UPD78F9502MA-CAC-A
Controller Family/series
UPD78F
No. Of I/o's
8
Ram Memory Size
128Byte
Cpu Speed
10MHz
No. Of Timers
2
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
4KB
Oscillator Type
External, Internal
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(2) External clock input circuit
Note Operation stop time is 277 s (MIN.), 544 s (TYP.), and 1.075 ms (MAX.).
If external clock input is selected by the option byte, the following is possible.
Figures 5-8 and 5-9 show the timing chart and status transition diagram of default start by external clock input.
(a) The internal reset signal is generated by the power-on clear function on power application, the option byte is
(b) The option byte is referenced and the system clock is selected. Then the external clock operates as the
High-speed operation
The accuracy of processing is improved as compared with high-speed internal oscillation (8 MHz (TYP.))
because an oscillation frequency of 1 MHz to 10 MHz can be selected and an external clock with a small
frequency deviation can be supplied.
referenced after reset, and the system clock is selected.
system clock.
System clock
Internal reset
CPU clock
RESET
V
DD
H
Figure 5-8. Timing of Default Start by External Clock Input
(a)
System clock is selected.
CHAPTER 5 CLOCK GENERATORS
(Operation stops
Preliminary User’s Manual U18681EJ1V0UD
Option byte is read.
Note
)
(b)
PCC = 02H, PPCC = 02H
External clock input
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