LM1881N National Semiconductor, LM1881N Datasheet - Page 5

• Manufacturer Part Number: LM1881N
• Description: IC, VIDEO SYNC SEPARATOR, 12V, 8-DIP
• Manufacturer: National Semiconductor

Specifications of LM1881N

• Output Synch Type: Composite, Vertical
• Supply Voltage Range: 5V To 12V
• Supply Current: 5.5mA
• Tv / Video Case Style: DIP
• No. Of Pins: 8
• Operating Temperature Range: 0°C To +70°C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Application Notes
ence called V
have a common input at their noninverting input coming from
the internal integrator. The internal integrator is used for
integrating the composite sync signal. This signal comes
from the input side of the composite sync buffer and are
positive going sync pulses. The capacitor to the integrator is
internal to the LM1881. The capacitor charge current is set
by the value of the external resistor R
integrator is going to be at a low voltage during the normal
horizontal lines because the integrator has a very short time
to charge the capacitor, which is during the horizontal sync
period. The equalization pulses will keep the output voltage
of the integrator at about the same level, below the V
During the vertical sync period the narrow going positive
pulses shown in Figure 1 is called the serration pulse. The
wide negative portion of the vertical sync period is called the
vertical sync pulse. At the start of the vertical sync period,
before the first Serration pulse occurs, the integrator now
charges the capacitor to a much higher voltage. At the first
serration pulse the integrator output should be between V
and V
comparator with V
into the “D” flip-flop by the falling edge of the serration pulse
(remember the sync signal is inverted in this section of the
LM1881). The “Q” output of the “D” flip-flop goes through the
OR gate, and sets the R/S flip-flop. The output of the R/S
flip-flop enables the internal oscillator and also clocks the
ODD/EVEN “D” flip-flop. The ODD/EVEN field pulse opera-
tion is covered in the next section. The output of the oscilla-
tor goes to a divide by 8 circuit, thus resetting the R/S
flip-flop after 8 cycles of the oscillator. The frequency of the
oscillator is established by the internal capacitor going to the
oscillator and the external R
flip-flop goes to pin 3 and is the actual vertical sync output of
the LM1881. By clocking the “D” flip-flop at the start of the
first serration pulse means that the vertical sync output pulse
starts at this point in time and lasts for eight cycles of the
internal oscillator as shown in Figure 1.
How R
shown under the Typical Performance Characteristics. The
first graph is “R
Pulse Separation”. For this graph to be valid, the vertical
sync pulse should last for at least 85% of the horizontal half
line (47% of a full horizontal line). A vertical sync pulse from
any standard should meet this requirement; both NTSC and
PAL do meet this requirement (the serration pulse is the
remainder of the period, 10% to 15% of the horizontal half
line). Remember this pulse is a positive pulse at the integra-
tor but negative in Figure 1. This graph shows how long it
takes the integrator to charge its internal capacitor above V
With R
be too small to charge the capacitor above V
be no vertical synch output pulse. As mentioned above, R
also sets the frequency of the internal oscillator. If the oscil-
lator runs too fast its eight cycles will be shorter than the
vertical sync portion of the composite sync. Under this con-
dition another vertical sync pulse can be generated on one of
the later serration pulse after the divide by 8 circuit resets the
R/S flip-flop. The first graph also shows the minimum R
necessary to prevent a double vertical pulse, assuming that
the serration pulses last for only three full horizontal line
periods (six serration pulses for NTSC). The actual pulse
width of the vertical sync pulse is shown in the “Vertical
Pulse Width vs R
2
SET
SET
. This would give a high level at the output of the
too large the charging current of the integrator will
affects the integrator and the internal oscillator is
2
going to one of its inputs. Both comparators
SET
SET
1
as one of its inputs. This high is clocked
” graph. Using NTSC as an example,
Value Selection vs Vertical Serration
SET
. The “Q” output of the R/S
(Continued)
SET
. The output of the
1
, thus there will
SET
SET
1
1
1
.
.
5
lets see how these two graphs relate to each other. The
Horizontal line is 64 µs long, or 32 µs for a horizontal half
line. Now round this off to 30 µs. In the “R
vs Vertical Serration Pulse Separation” graph the minimum
resistor value for 30 µs serration pulse separation is about
550 kΩ. Going to the “Vertical Pulse Width vs R
one can see that 550 kΩ gives a vertical pulse width of about
180 µs, the total time for the vertical sync period of NTSC (3
horizontal lines). A 550 kΩ will set the internal oscillator to a
frequency such that eight cycles gives a time of 180 µs, just
long enough to prevent a double vertical sync pulse at the
vertical sync output of the LM1881.
The LM1881 also generates a default vertical sync pulse
when the vertical sync period is unusually long and has no
serration pulses. With a very long vertical sync time the
integrator has time to charge its internal capacitor above the
voltage level V
a serration pulse to clock the “D” flip-flop, the only high signal
going to the OR gate is from the default comparator when
output of the integrator reaches V
flip-flop is toggled by the default comparator, starting the
vertical sync pulse at pin 3 of the LM1881. If the default
vertical sync period ends before the end of the input vertical
sync period, then the falling edge of the vertical sync (posi-
tive pulse at the “D” flip-flop) will clock the high output from
the comparator with V
ger the oscillator, generating a second vertical sync output
pulse. The “Vertical Default Sync Delay Time vs R
shows the relationship between the R
delay time from the start of the vertical sync period before
the default vertical sync pulse is generated. Using the NTSC
example again the smallest resistor for R
vertical default time delay is about 50 µs, much longer than
the 30 µs serration pulse spacing.
A common question is how can one calculate the required
R
pulses during the vertical blanking. If the default vertical sync
is to be used this is a very easy task. Use the “Vertical
Default Sync Delay Time vs R
essary R
sync output signal. If a second pulse is undesirable, then
check the “Vertical Pulse Width vs R
the vertical output pulse will extend beyond the end of the
input vertical sync period. In most systems the end of the
vertical sync period may be very accurate. In this case the
preferred design may be to start the vertical sync pulse at the
end of the vertical sync period, similar to starting the vertical
sync pulse after the first serration pulse. A VGA standard is
to be used as an example to show how this is done. In this
standard a horizontal line is 32 µs long. The vertical sync
period is two horizontal lines long, or 64 µs. The vertical
default sync delay time must be longer than the vertical
sync period of 64 µs. In this case R
680 kΩ. R
integrator to reach V
the input pulse. The first graph can be used to confirm that
R
vertical serration pulse separation, use the actual pulse
width of the vertical sync period, or 64 µs in this example.
This graph is linear, meaning that a value as large as 2.7 MΩ
can be used for R
30 µs). Due to leakage currents it is advisable to keep the
value of R
MΩ is selected, well above the minimum of 680 kΩ. With this
value for R
pulse of the LM1881 is about 340 µs.
SET
SET
is small enough for the integrator. Instead of using the
with a video timing standard that has no serration
SET
SET
SET
SET
to give the desired delay time for the vertical
must still be small enough for the output of the
under 2.0 MΩ. In this example a value of 1.0
2
. Since there is no falling edge at the end of
the pulse width of the vertical sync output
SET
1
before the end of the vertical period of
1
(twice the value as the maximum at
as a reference input. This will retrig-
SET
” graph to select the nec-
SET
2
SET
. At this time the R/S
” graph to make sure
must be larger than
SET
SET
SET
Value Selection
value and the
is 500 kΩ. The
www.national.com
SET
SET
” graph
” graph