DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1013
DS72030W200FPV
Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet
1.R5S72030W200FP.pdf
(1686 pages)
Specifications of DS72030W200FPV
Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 1013 of 1686
- Download datasheet (10Mb)
Bit 2 — Timer Compare Match Flag 1 (TSR2): Indicates that a Compare-Match condition
occurred to the Timer Compare Match Register 1 (TCMR1). When the value set in the TCMR1
matches to Cycle Time Register (TCMR1 = CYCTR), this bit is set if TTCR0 bit11 = 1. Please
note that this bit is read-only and is cleared when IRR15 (Timer Compare Match Interrupt 1) is
cleared.
Bit 1 — Timer Compare Match Flag 0 (TSR1): Indicates that a Compare-Match condition
occurred to the Compare Match Register 0 (TCMR0). When the value set in the TCMR0 matches
to the Timer value (TCMR0 = TCNTR), this bit is set if TTCR0 bit10 = 1. Please note that this bit
is read-only and is cleared when IRR14 (Timer Compare Match Interrupt 0) is cleared.
Bit 0 — Timer Overrun/Next_is_Gap Reception/Message Error (TSR0): This flag is assigned
to three different functions. It indicates that the Timer has overrun when working in event-trigger
mode, time reference message with Next_is_Gap set has been received in time-trigger mode, and
error detected on the CAN bus has occurred in test mode, respectively. Test mode has higher
priority with respect to the other settings.
Bit3: TSR3
0
1
Bit2: TSR2
0
1
Bit1: TSR1
0
1
Description
Timer Compare Match has not occurred to the TCMR2 (Initial value)
[Clearing condition] Writing ‘1’ to IRR11 (Timer Compare Match Interrupt 1)
Timer Compare Match has occurred to the TCMR2
[Setting condition]
TCMR2 matches to Cycle Time (TCMR2 = CYCTR), if TTCR0 bit12 = 1.
Description
Timer Compare Match has not occurred to the TCMR1 (Initial value)
[Clearing condition] Writing ‘1’ to IRR15 (Timer Compare Match Interrupt 1)
Timer Compare Match has occurred to the TCMR1
[Setting condition]
TCMR1 matches to Cycle Time (TCMR1 = CYCTR), if TTCR0 bit11 = 1.
Description
Compare Match has not occurred to the TCMR0 (Initial value)
[Clearing condition] Writing ‘1’ to IRR14 (Timer Compare Match Interrupt 0)
Compare Match has occurred to the TCMR0
[Setting condition] TCMR0 matches to the Timer value (TCMR0 = TCNTR)
Section 19 Controller Area Network (RCAN-TL1)
Rev. 3.00 Sep. 28, 2009 Page 981 of 1650
REJ09B0313-0300
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