DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1015
DS72030W200FPV
Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet
1.R5S72030W200FP.pdf
(1686 pages)
Specifications of DS72030W200FPV
Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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(6)
This is a 16-bit read/write register that allows the CPU to monitor and modify the value of the
Free Running Timer Counter. When the Timer meets TCMR0 (Timer Compare Match Register 0)
+ TTCR0 [6] is set to ‘1’, the TCNTR is cleared to H'0000 and starts running again. In Time-
Trigger mode, this timer can be used as Local Time and TTCR0[6] has to be cleared to work as a
free running timer.
Notes: 1. It is possible to write into this register only when it is enabled by the bit 15 in TTCR0.
• TCNTR (Address = H'08C)
Note: * The register can be written only when enabled in TTCR0[15]. Write operation is not
Bits 15 to 0 — Indicate the value of the Free Running Timer.
(7)
This register is a 16-bit read-only register. This register shows Cycle Time = Local Time
(TCNTR) - Reference_Mark (RFMK). In ET mode this register is the exact copy of TCNTR as
RFMK is always fixed to zero.
• CYCTR (Address = H'090)
Initial value:
Initial value:
Timer Counter Register (TCNTR)
Cycle Time register (CYCTR)
R/W:
R/W:
Bit:
Bit:
2. There could be a delay of a few clock cycles between the enabling of the timer and the
If TTCR0 bit15 = 0, TCNTR is always H'0000.
moment where TCNTR starts incrementing. This is caused by the internal logic used
for the pre-scaler.
allowed in Time Trigger mode (i.e. CMAX is not 3'b111).
R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
15
15
R
0
0
14
14
R
0
0
13
13
R
0
0
12
12
R
0
0
11
11
R
0
0
10
10
R
0
0
R
9
0
9
0
CYCTR[15:0]
TCNTR[15:0]
R
8
0
8
0
Section 19 Controller Area Network (RCAN-TL1)
R
7
0
7
0
Rev. 3.00 Sep. 28, 2009 Page 983 of 1650
R
6
0
6
0
R
5
0
5
0
R
4
0
4
0
3
0
R
3
0
REJ09B0313-0300
2
0
R
2
0
1
0
R
1
0
0
0
R
0
0
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