DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1200
DS72030W200FPV
Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet
1.R5S72030W200FP.pdf
(1686 pages)
Specifications of DS72030W200FPV
Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 1200 of 1686
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Section 23 USB 2.0 Host/Function Module (USB)
Notes: 1. Reading of 0 and writing of 1 are valid.
Rev. 3.00 Sep. 28, 2009 Page 1168 of 1650
REJ09B0313-0300
Bit
9
8
7
6
5 to 2
1, 0
2. If the SQCLR and SQSET bits in this register and DCPCTR are being used to change
3. The SQCLR bit and SQSET bits should not be set to 1 at the same time. Before
Bit Name
ACLRM
SQCLR
SQSET
SQMON
⎯
PID
the data PID sequence toggle bit for several pipes in succession, an access cycle of
120 ns and 5- or more bus clock cycles is required.
operating either bit, PID = NAK should be set. If isochronous transfer is set for the
transfer type (TYPE = 11), writing to the SQSET bit is invalid.
Initial
Value
0
0
0
0
All 0
00
R/W
R/W
R/W*
R/W*
R
R
R/W
1
1
Description
Auto Buffer Clear Mode
0: Disabled
1: Enabled (all buffers are initialized)
ACLRM = 1 should not be set for the pipe which has
been selected by the CURPIPE bits in
CFIFOSEL/DnFIFOSEL.
Toggle Bit Clear*
0: Invalid
1: Specifies DATA0
Toggle Bit Set*
0: Invalid
1: Specifies DATA1
Toggle Bit Confirmation
0: DATA0
1: DATA1
Reserved
These bits are always read as 0. The write value
should always be 0.
Response PID*
00: NAK response
01: BUF response (depending on the buffer state)
10: STALL response
11: STALL response
When the host controller function is selected and PID
is not set to BUF, no token is issued. If a transfer
error is detected, the controller sets the PID bits to
end the transfer.
2
3
*
3
2
*
3
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