DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1445
DS72030W200FPV
Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet
1.R5S72030W200FP.pdf
(1686 pages)
Specifications of DS72030W200FPV
Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Note:
28.2.9
SYSCR3 is an 8-bit readable/writable register that performs the software reset control for the SSI0
to SSI3 and the operation of the crystal resonator for audio. Only byte access is valid.
Note: When writing to this register, see section 28.4, Usage Notes.
Bit
2
1
0
Bit
7
* For addresses in each page, see section 27, On-Chip RAM.
System Control Register 3 (SYSCR3)
Bit Name
RAMWE2
RAMWE1
RAMWE0
Bit Name
AXTALE
Initial value:
Initial
Value
1
1
1
Initial
Value
0
R/W:
Bit:
R/W
AXT
ALE
7
0
R/W
R/W
R/W
R/W
R/W
R/W
R
6
0
-
Description
RAM Write Enable 2 (corresponding area of on-chip
RAM (high-speed): page 2*)
0: Write to on-chip RAM (high-speed) disabled
1: Write to on-chip RAM (high-speed) enabled
RAM Write Enable 1 (corresponding area of on-chip
RAM (high-speed): page 1*)
0: Write to on-chip RAM (high-speed) disabled
1: Write to on-chip RAM (high-speed) enabled
RAM Write Enable 0 (corresponding area of on-chip
RAM (high-speed): page 0*)
0: Write to on-chip RAM (high-speed) disabled
1: Write to on-chip RAM (high-speed) enabled
Description
AUDIO_X1 Clock Control
Controls the function of AUDIO_X1 pin.
0: Runs the on-chip crystal oscillator/enables the
1: Halts the on-chip crystal oscillator/disables the
R
5
0
-
external clock input.
external clock input.
R
4
0
-
SRST
SSI3
R/W
3
0
Rev. 3.00 Sep. 28, 2009 Page 1413 of 1650
SRST
SSI2
R/W
2
0
SRST
R/W
SSI1
1
0
Section 28 Power-Down Modes
SRST
SSI0
R/W
0
0
REJ09B0313-0300
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