DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 15
DS72030W200FPV
Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet
1.R5S72030W200FP.pdf
(1686 pages)
Specifications of DS72030W200FPV
Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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7.4
7.5
Section 8 Cache..................................................................................................219
8.1
8.2
8.3
8.4
Section 9 Bus State Controller (BSC)................................................................239
9.1
9.2
9.3
9.4
Operation ........................................................................................................................... 210
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
Usage Notes ....................................................................................................................... 217
Features.............................................................................................................................. 219
8.1.1
Register Descriptions ......................................................................................................... 222
8.2.1
8.2.2
Operation ........................................................................................................................... 228
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
Memory-Mapped Cache .................................................................................................... 234
8.4.1
8.4.2
8.4.3
8.4.4
Features.............................................................................................................................. 239
Input/Output Pins ............................................................................................................... 242
Area Overview ................................................................................................................... 244
9.3.1
9.3.2
Register Descriptions ......................................................................................................... 246
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
Flow of the User Break Operation ........................................................................ 210
Break on Instruction Fetch Cycle.......................................................................... 211
Break on Data Access Cycle................................................................................. 212
Value of Saved Program Counter ......................................................................... 213
Usage Examples.................................................................................................... 214
Cache Structure..................................................................................................... 219
Cache Control Register 1 (CCR1) ........................................................................ 222
Cache Control Register 2 (CCR2) ........................................................................ 224
Searching Cache ................................................................................................... 228
Read Access.......................................................................................................... 230
Prefetch Operation (Only for Operand Cache) ..................................................... 230
Write Operation (Only for Operand Cache).......................................................... 231
Write-Back Buffer (Only for Operand Cache)...................................................... 231
Coherency of Cache and External Memory .......................................................... 233
Address Array ....................................................................................................... 234
Data Array ............................................................................................................ 235
Usage Examples.................................................................................................... 237
Notes ..................................................................................................................... 238
Address Map ......................................................................................................... 244
Data Bus Width and Pin Function Setting in Each Area....................................... 245
Common Control Register (CMNCR) .................................................................. 247
CSn Space Bus Control Register (CSnBCR) (n = 0 to 7) ..................................... 250
CSn Space Wait Control Register (CSnWCR) (n = 0 to 7) .................................. 255
SDRAM Control Register (SDCR)....................................................................... 289
Refresh Timer Control/Status Register (RTCSR) ................................................. 293
Refresh Timer Counter (RTCNT)......................................................................... 295
Rev. 3.00 Sep. 28, 2009 Page xiii of xxx
REJ09B0313-0300
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