DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 239
DS72030W200FPV
Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet
1.R5S72030W200FP.pdf
(1686 pages)
Specifications of DS72030W200FPV
Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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7.3.6
BRCR sets the following conditions:
1. Specifies whether a start of user break interrupt exception processing by instruction fetch cycle
2. Specifies the pulse width of the UBCTRG output when a break condition is satisfied.
3. Specifies whether a trigger signal is output to the UBCTRG pin when a break condition is
BRCR is a 32-bit readable/writable register that has break condition match flags and bits for
setting other break conditions. For the condition match flags of bits 15 to 12, writing 1 is invalid
(previous values are retained) and writing 0 is only possible. To clear the flag, write 0 to the flag
bit to be cleared and 1 to all other flag bits.
Bit
1, 0
Initial value:
Initial value:
Bit
31 to 20
is set before or after instruction execution.
satisfied.
R/W:
R/W:
Bit:
Bit:
Break Control Register (BRCR)
Bit Name
SZ[1:0]
SCMFC
Bit Name
⎯
R/W
31
15
R
0
0
-
0
SCMFC
R/W
30
14
R
0
0
-
1
SCMFD
R/W
29
13
R
0
0
-
0
Initial
Value
Initial
Value
All 0
00
SCMFD
R/W
28
12
R
0
1
0
-
27
11
R
R
0
0
-
-
R/W
R/W
R/W
R
26
10
R
R
0
0
-
-
Description
Select the operand size of the bus cycle for the break
condition.
00: Break condition does not include operand size
01: Break condition is byte access
10: Break condition is word access
11: Break condition is longword access
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Operand Size Select
25
R
R
0
9
0
-
-
24
R
R
0
8
0
-
-
23
R
R
0
7
0
-
-
Rev. 3.00 Sep. 28, 2009 Page 207 of 1650
PCB1 PCB0
R/W
22
R
0
6
0
-
Section 7 User Break Controller (UBC)
R/W
21
R
0
5
0
-
20
R
R
0
4
0
-
-
UTOD1 UTOD0
R/W
19
R
0
3
0
-
REJ09B0313-0300
R/W
18
R
0
2
0
-
R/W
17
R
CKS[1:0]
0
1
0
-
R/W
16
R
0
0
0
-
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