DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 251
DS72030W200FPV
Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet
1.R5S72030W200FP.pdf
(1686 pages)
Specifications of DS72030W200FPV
Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8.1
• Capacity
• Structure: Instructions/data separated, 4-way set associative
• Way lock function (operand cache only): Way 2 and way 3 are lockable
• Line size: 16 bytes
• Number of entries: 128 entries/way
• Write system: Write-back/write-through selectable
• Replacement method: Least-recently-used (LRU) algorithm
8.1.1
The cache separates data and instructions and uses a 4-way set associative system. It is composed
of four ways (banks), each of which is divided into an address section and a data section.
Each of the address and data sections is divided into 128 entries per way. The data section of the
entry is called a line. Each line consists of 16 bytes (4 bytes × 4). The data capacity per way is 2
Kbytes (16 bytes × 128 entries), with a total of 8 Kbytes in the cache as a whole (4 ways). Figure
8.1 shows the operand cache structure. The instruction cache structure is the same as the operand
cache structure except for not having the U bit.
Instruction cache: 8 Kbytes
Operand cache: 8 Kbytes
Features
Cache Structure
Section 8 Cache
Rev. 3.00 Sep. 28, 2009 Page 219 of 1650
REJ09B0313-0300
Section 8 Cache
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