DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 385
DS72030W200FPV
Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet
1.R5S72030W200FP.pdf
(1686 pages)
Specifications of DS72030W200FPV
Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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(11) Power-Down Mode
If the PDOWN bit in SDCR is set to 1, the SDRAM is placed in power-down mode by bringing
the CKE signal to the low level in the non-access cycle. This power-down mode can effectively
lower the power consumption in the non-access cycle. However, please note that if an access
occurs in power-down mode, a cycle of overhead occurs because a cycle is needed to assert the
CKE in order to cancel the power-down mode.
Figure 9.31 shows the access timing in power-down mode.
RASL, RASU
CASL, CASU
A12/A11*
D31 to D0
A25 to A0
DACKn*
RD/WR
DQMxx
CKIO
CKE
CSn
BS
1
2
Power-down
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
Figure 9.31 Power-Down Mode Access Timing
2. The waveform for DACKn is when active low is specified.
Tnop
Tr
Tc1
Td1
Rev. 3.00 Sep. 28, 2009 Page 353 of 1650
Tde
Section 9 Bus State Controller (BSC)
Tap
Power-down
REJ09B0313-0300
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