DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 554
DS72030W200FPV
Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet
1.R5S72030W200FP.pdf
(1686 pages)
Specifications of DS72030W200FPV
Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Note:
11.3.30 Bus Master Interface
The timer counters (TCNT), general registers (TGR), timer subcounter (TCNTS), timer cycle
buffer register (TCBR), timer dead time data register (TDDR), timer cycle data register (TCDR),
timer A/D converter start request control register (TADCR), timer A/D converter start request
cycle set registers (TADCOR), and timer A/D converter start request cycle set buffer registers
(TADCOBR) are 16-bit registers. A 16-bit data bus to the bus master enables 16-bit read/writes. 8-
bit read/write is not possible. Always access in 16-bit units.
All registers other than the above registers are 8-bit registers. These are connected to the CPU by a
16-bit data bus, so 16-bit read/writes and 8-bit read/writes are both possible.
Rev. 3.00 Sep. 28, 2009 Page 522 of 1650
REJ09B0313-0300
Bit
0
* Do not set to 1 when complementary PWM mode is not selected.
Bit Name
WRE
Initial
Value
0
R/W
R/(W)
Description
Waveform Retain Enable
Selects the waveform output when synchronous
counter clearing occurs in complementary PWM mode.
The output waveform is retained only when
synchronous clearing occurs within the Tb interval at
the trough in complementary PWM mode. When
synchronous clearing occurs outside this interval, the
initial value specified in TOCR is output regardless of
the WRE bit setting. The initial value is also output
when synchronous clearing occurs in the Tb interval at
the trough immediately after TCNT_3 and TCNT_4 start
operation.
For the Tb interval at the trough in complementary
PWM mode, see figure 11.40.
0: Outputs the initial value specified in TOCR
1: Retains the waveform output immediately before
[Setting condition]
•
synchronous clearing
When 1 is written to WRE after reading WRE = 0
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