DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 759
DS72030W200FPV
Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet
1.R5S72030W200FP.pdf
(1686 pages)
Specifications of DS72030W200FPV
Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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15.3.1
SCRSR receives serial data. Data input at the RxD pin is loaded into SCRSR in the order received,
LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is
automatically transferred to the receive FIFO data register (SCFRDR).
The CPU cannot read or write to SCRSR directly.
15.3.2
SCFRDR is a 16-byte FIFO register that stores serial receive data. The SCIF completes the
reception of one byte of serial data by moving the received data from the receive shift register
(SCRSR) into SCFRDR for storage. Continuous reception is possible until 16 bytes are stored.
The CPU can read but not write to SCFRDR. If data is read when there is no receive data in the
SCFRDR, the value is undefined.
When SCFRDR is full of receive data, subsequent serial data is lost.
Receive Shift Register (SCRSR)
Receive FIFO Data Register (SCFRDR)
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
R
7
7
-
-
-
R
6
6
-
-
-
Section 15 Serial Communication Interface with FIFO (SCIF)
R
5
5
-
-
-
R
4
4
-
-
-
R
3
3
-
-
-
Rev. 3.00 Sep. 28, 2009 Page 727 of 1650
R
2
2
-
-
-
R
1
1
-
-
-
R
0
0
-
-
-
REJ09B0313-0300
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