DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 777
DS72030W200FPV
Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet
1.R5S72030W200FP.pdf
(1686 pages)
Specifications of DS72030W200FPV
Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 777 of 1686
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• Clock synchronous mode:
B:
N:
Pφ:
n:
Table 15.3 SCSMR Settings
The bit rate error in asynchronous mode is given by the following formula:
n
0
1
2
3
N =
Bit rate (bits/s)
SCBRR setting for baud rate generator (0 ≤ N ≤ 255)
(The setting must satisfy the electrical characteristics.)
Operating frequency for peripheral modules (MHz)
Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n,
see table 15.3.)
When baud rate generator operates in normal mode (the BGDM bit of SCEMR is 0):
When baud rate generator operates in double speed mode (the BGDM bit of SCEMR is 1):
Error (%) =
Error (%) =
Error (%) =
Error (%) =
8 × 2
Pφ
2n-1
× B
(N + 1) × B × 64 × 2
(N + 1) × B × 32× 2
(N + 1) × B × 32× 2
(N + 1) × B × 16× 2
Clock Source
Pφ
Pφ/4
Pφ/16
Pφ/64
× 10
Pφ × 10
Pφ × 10
Pφ × 10
Pφ × 10
6
− 1
6
6
6
6
2n-1
2n-1
2n-1
2n-1
Section 15 Serial Communication Interface with FIFO (SCIF)
− 1
− 1
− 1
− 1
CKS[1]
0
0
1
1
× 100 (Operation on a base clock with a frequency of
× 100 (Operation on a base clock with a frequency of
× 100 (Operation on a base clock with a frequency of
× 100 (Operation on a base clock with a frequency of
16 times the bit rate)
16 times the bit rate)
8 times the bit rate)
8 times the bit rate)
Rev. 3.00 Sep. 28, 2009 Page 745 of 1650
SCSMR Settings
CKS[0]
0
1
0
1
REJ09B0313-0300
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