DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 91
DS72030W200FPV
Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet
1.R5S72030W200FP.pdf
(1686 pages)
Specifications of DS72030W200FPV
Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Addressing
Mode
Register indirect
with
displacement
Register indirect
with
displacement
Indexed register
indirect
GBR indirect
with
displacement
Instruction
Format
@(disp:4,
Rn)
@(disp:12,
Rn)
@(R0,Rn)
@(disp:8,
GBR)
Effective Address Calculation
The effective address is the sum of Rn and a 4-bit
displacement (disp). The value of disp is zero-
extended, and remains unchanged for a byte
operation, is doubled for a word operation, and is
quadrupled for a longword operation.
The effective address is the sum of Rn and a 12-
bit
displacement (disp). The value of disp is zero-
extended.
The effective address is the sum of Rn and R0.
The effective address is the sum of GBR value
and an 8-bit displacement (disp). The value of
disp is zero-extended, and remains unchanged for
a byte operation, is doubled for a word operation,
and is quadrupled for a longword operation.
(zero-extended)
(zero-extended)
(zero-extended)
1/2/4
Rn
R0
disp
GBR
1/2/4
disp
Rn
disp
Rn
×
×
+
+
+
+
Rn + disp × 1/2/4
+ disp × 1/2/4
Rn + disp
Rn + R0
Rev. 3.00 Sep. 28, 2009 Page 59 of 1650
GBR
REJ09B0313-0300
Equation
Byte:
Rn + disp
Word:
Rn + disp × 2
Byte:
Rn + disp
Word:
Rn + disp
Longword:
Rn + disp
Rn + R0
Longword:
Rn + disp × 4
Byte:
GBR + disp
Word:
GBR + disp × 2
Longword:
GBR + disp × 4
Section 2 CPU
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