H27US08121B-TPCB HYNIX SEMICONDUCTOR, H27US08121B-TPCB Datasheet
H27US08121B-TPCB
Specifications of H27US08121B-TPCB
Related parts for H27US08121B-TPCB
H27US08121B-TPCB Summary of contents
Page 1
Document Title 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Memory Revision History No. 0.0 Initial Draft 0.1 Renewal Product Group 0.2 Make a decision of PKG information 0.3 Append 1.8V Operation Product to Data sheet 1) Add Errata tWC Specification 50 ...
Page 2
FEATURES SUMMARY HIGH DENSITY NAND FLASH MEMORIES - Cost effective solutions for mass storage applications NAND INTERFACE - x8 or x16 bus width. - Multiplexed Address/ Data - Pinout compatibility for all densities SUPPLY VOLTAGE - 3.3V device: VCC = ...
Page 3
DESCRIPTION The HYNIX HY27(U/S)SXX121M series is a family of non-volatile Flash memories that use NAND cell technology. The devices operate 3.3V and 1.8V voltage supply. The size of a Page is either 528 Bytes (512 + 16 spare) or 264 ...
Page 4
Vcc CE RE NAND WE Flash ALE CLE WP Vss Figure 1: Logic Diagram Address Register/Counter ALE CLE Command WE Interface CE Logic WP RE Command Register Rev 0.6 / Oct. 2004 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash I/O I/O ...
Page 5
NAND Flash ...
Page 6
Figure 5. 63-FBGA Contactions, x8 Device (Top view through package ...
Page 7
MEMORY ARRAY ORGANIZATION The memory array is made up of NAND structures where 16 cells are connected in series. The memory array is organized in blocks where each block contains 32 pages. The array is split into two areas, the ...
Page 8
SIGNAL DESCRIPTIONS See Figure 1, Logic Diagram and Table 1, Signal Names, for a brief overview of the signals connected to this device. Inputs/Outputs (I/O -I Input/Outputs are used to input the selected address, ...
Page 9
Ready/Busy (RB) The Ready/Busy output, RB open-drain output that can be used to identify if the Program/ Erase/ Read (PER) Controller is currently active. When Ready/Busy is Low read, program or erase operation is in ...
Page 10
Data Output Data Output bus operations are used to read: the data in the memory array, the Status Register, the Electronic Signa- ture and the Serial Number. Data is output when Chip Enable is Low, Write Enable is High, Address ...
Page 11
Table 2. Bus Operation BUS Operation CE Command Input V IL Address Input V IL Data Input V IL Data Output V IL Write Protect X Standby V IH Note : (1) Only for x16 devices. (2) WP must be ...
Page 12
COMMAND SET All bus write operations to the device are interpreted by the Command Interface. The Commands are input on I/O O and are latched on the rising edge of Write Enable when the Command Latch Enable signal is high. ...
Page 13
However, the Read B command is effective for only one operation, once an operation has been executed in Area B the pointer returns automatically to Area A. The pointer operations can also be used before a ...
Page 14
Read Memory Array Each operation to read the memory area starts with a pointer operation as shown in the Pointer Operations section. The device defaults to Read A mode after powerup or a Reset operation. Devices, where page0 is read ...
Page 15
CLE CE WE ALE RE RB 00h/ I/O 01h/ 50h Command Code Note less than 10ns, t ELWL Read A Command, x8 Devices Area A (1st half Page) A9-A25(1) A0-A7 Read B Command, x8 Devices Area ...
Page 16
Busy time) RB 00h/ I/O Address Inputs 01h/50h Command Code Read A Command, x8 Devices Read A Command, x8 Devices Read A Command, x8 Devices Area A Area A Area A Area A Area B Area B Area B ...
Page 17
Page Program The Page Program operation is the standard operation to program data to the memory array. The main area of the memory array is programmed by page, however partial page programming is allowed where any number of bytes (1 ...
Page 18
Copy Back Program The Copy Back Program operation is used to copy the data stored in one page and reprogram it in another page. The Copy Back Program operation does not require external memory and so the operation is faster ...
Page 19
Once the erase operation has completed the Status Register can be checked for errors. RB Block Address I/O 60h Inputs Block Erase Setup Code Reset The Reset command is used to reset the Command Interface and Status Register. If the ...
Page 20
P/E/R Controller Status Register bit SR6 has two different functions depending on the current operation. During all other operations SR6 acts as a P/E/R Controller bit, which indicates whether the P/E/R Controller is active or inactive. When the P/E/R Controller ...
Page 21
Table 6: Status Register Bit Bit SR7 Write Protection Program/Erase/Read SR6 Program/ Erase/ Read SR5 SR4, SR3, SR2 SR0 Generic Error Read Electronic Signature The device contains a Manufacturer Code and Device Code. To read these codes two steps are ...
Page 22
Sequential Row Read Disabled If the device is delivered with Sequential row read disabled and Automatic Read Page 0 at Power-up, only the first page (Page 0) will be automatically read after the power-on sequence. Refer to Figure 18. Sequential ...
Page 23
Vccth(1) Vcc WE CE ALE CLE tBLBH1 (Read Busy time) RB Busy I/O Note: (1 equal to 2.5V for 3.3V Power Supply devices and to 1.5V for 1.8V Power Supply devices. CCth Figure 19. Automatic Page 0 Read ...
Page 24
Block Address= Table 8: Valid Block Symbol Valid Block VB PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES The Program and Erase times and the number of Program/ Erase cycles per block are shown in Table 9. Rev ...
Page 25
Table 9: Program, Erase Time and Program Erase Endurance Cycles Parameters Page Program Time Block Erase Time Program/Erase Cycles (per block) Data Retention MAXIMUM RATING Stressing the device above the ratings listed in Table 10, Absolute Maximum Ratings, may cause ...
Page 26
Table 11: Operating and AC Measurement Conditions Parameter Supply Voltage ( Ambient Temperature (T A Load Capacitance ( TTL GATE and C L Input Pulses Voltages Input and Output Timing Ref. Voltages Input Rise and Fall ...
Page 27
Table 13: DC Characteristics, 3.3V Device and 1.8V Device Sym- Parameter bol Sequentia I CC1 Read Operating I Current Program CC2 I Erase CC3 I Stand-by Current (TTL) CC4 Stand-By Current I CC5 (CMOS) I Input Leakage Current LI I ...
Page 28
Table 14: AC Characteristics for Command, Address, Data Input (3.3V and 1.8V Device) Alt. Symbol Symbol t Address Latch Low to Write Enable Low ALLWL t ALS t Address Latch Hith to Write Enable Low ALHWL t Command Latch High ...
Page 29
Table 15: AC Characteristics for Operation (3.3V Device and 1.8V Device) Alt. Sym- Sym- bol bol t t ALLRL1 AR1 Address Latch Low to Read Enable Low t t ALLRL2 AR2 t t Ready/Busy High to Read Enable Low BHRL ...
Page 30
Alt. Sym- Sym- bol bol t t Write Enable High to Read Enable Low WHRL WHR Write Enable Low to Write Enable t t WLWL WC Low Note: (1). The time to Ready depends on the value of the pull-up ...
Page 31
Setup time) CLE tELWL (CE Setup time) CE tWLWH WE tALHWL tWHWL (ALE Setup time) tWHALL (ALE Hold time) ALE tDVWH (Data Setup time) Address I/O CLE CE tALLWL (ALE Setup time) ALE tWLWH WE tDVWH (Data Setup ...
Page 32
CE (RE High Holdtime) RE tRLQV (RE Accesstime) I/O tBHRL RB Figure 24. Sequential Data Output after Read AC Waveforms Note:1. CLE = Low, ALE = Low High. CLE tCLHWL CE tELWL WE RE tDVWH (Data Setup time) ...
Page 33
CLE CE WE ALE RE I/O 90h Read Electronic Signature Command Figure 26. Read Electronic Signature AC Waveform Note: Refer to table(To see Page 22) for the values of the manufacture and device codes. CLE CE tWHWL WE ALE RE ...
Page 34
CLE CE WE ALE RE Add. M 50h I/O cycle 1 RB Command Code Figure 28. Read C Operation, One Page AC Waveform Note: 1. A0-A7 is the address in the Spare Memory area, where A0-A3 are valid and A4-A7 ...
Page 35
CLE CE tWLWL (Write Cycle time) WE ALE RE Add. N I/O 80h cycle 1 RB Page Program Setup Code Rev 0.6 / Oct. 2004 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash tWLWL Add. N Add cycle 2 cycle ...
Page 36
CLE CE tWLWL (Write Cycle time) WE ALE RE Add. N Add. N I/O 60h cycle 1 cycle 2 RB Block Erase Block Address Input Setup Command WE ALE CLE RE I/O FFh RB Rev 0.6 / Oct. 2004 512Mbit ...
Page 37
System Interface Using CE don’t care To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below. So possible to connect NAND Flash to a microprocessor. The only function that was removed ...
Page 38
Ready/Busy Signal Electrical Characteristics Figures 32, 33 and 34 show the electrical characteristics for the Ready/Busy signal. The value required for the resistor R can be calculated using the following equation: P where I is the sum of the input ...
Page 39
Figure 36. Resistor Value Waveform Timings for Ready/Busy Signal Rev 0.6 / Oct. 2004 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Vcc=1.8, CL=30pF 1.7 0. 1.7 1.7 2 ...
Page 40
Figure 37. 48-TSOP1 - 48-lead Plastic Thin Small Outline 20mm, Package Outline Table 16: 48-TSOP1 - 48-lead Plastic Thin Small Outline 20mm, Package Mechanical Data Symbol Min A A1 0.050 A2 0.980 B 0.170 C 0.100 ...
Page 41
Figure 38. 48-WSOP1 - 48-lead Plastic Very Very Thin Small Outline 17mm, Package Outline Table 17: 48-WSOP1 - 48-lead Plastic Thin Small Outline 17mm, Package Mechanical Data Symbol ...
Page 42
Figure 39. 63-FBGA - 8.5 x 15mm, 6x8 ball array 0.8mm pitch, Pakage Outline Note: Drawing is not to scale. Table 17: 48-WSOP1 - 48-lead Plastic Thin Small Outline 17mm, Package Mechanical Data Symbol ...
Page 43
MARKING INFORMATION Package TSOP1 / WSOP1 / FBGA - hynix - KOR - HY27xSxx121mTxB HY: HYNIX 27: NAND Flash x: Power Supply S: Classification xx: Bit Organization 12: Density 1: Mode M: Version x: Package Type x: Package Material x: ...