IS62WV5128BLL-55HLI INTEGRATED SILICON SOLUTION (ISSI), IS62WV5128BLL-55HLI Datasheet - Page 9

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IS62WV5128BLL-55HLI

Manufacturer Part Number
IS62WV5128BLL-55HLI
Description
SRAM, 512K X 8, 3V, 55NS, 32STSOP1
Manufacturer
INTEGRATED SILICON SOLUTION (ISSI)
Datasheet

Specifications of IS62WV5128BLL-55HLI

Memory Size
4Mbit
Access Time
55ns
Supply Voltage Range
2.5V To 3.6V
Memory Case Style
TSOP-1
No. Of Pins
32
Operating Temperature Range
-40°C To +85°C
Memory Configuration
512K X 8
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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IS62WV5128ALL,
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
01/29/08
WRITE CYCLE SWITCHING CHARACTERISTICS
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V to
2. The internal write time is defined by the overlap of CS1 LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS1 Controlled, OE = HIGH or LOW)
Symbol
t
t
t
t
t
t
t
t
t
t
V
terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
WC
SCS1
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
DD
ADDRESS
-0.2V/V
(3)
(3)
DOUT
CS1
DIN
DD
WE
-0.3V and output loading specified in Figure 1.
Parameter
Write Cycle Time
CS1 to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
IS62WV5128BLL
t
DATA UNDEFINED
SA
t
AW
t
HZWE
t
SCS1
t
WC
t
PWE
(1,2)
HIGH-Z
(Over Operating Range)
t
SD
DATA-IN VALID
Min.
45
45
40
25
55
0
0
5
0
55 ns
Max.
t
20
HA
t
t
LZWE
HD
Min.
70
60
60
30
50
0
0
0
5
70 ns
Max.
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9

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