FM25CL64-G Ramtron, FM25CL64-G Datasheet - Page 2

• Manufacturer Part Number: FM25CL64-G
• Description: IC, FRAM, 64KBIT, 20MHZ, SOIC-8
• Manufacturer: Ramtron

Specifications of FM25CL64-G

• Memory Size: 64Kbit
• Memory Configuration: 8K X 8
• Ic Interface Type: Serial, SPI
• Supply Voltage Range: 2.7V To 3.65V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Descriptions
Rev. 3.5
Feb. 2011
Pin Name
/CS
SCK
/HOLD
/WP
SI
SO
VDD
VSS
HOLD
SCK
WP
CS
SI
Output
Supply
Supply
Input
Input
Input
Input
Input
I/O
Description
Chip Select: This active low input activates the device. When high, the device enters
low-power standby mode, ignores other inputs, and all outputs are tri-stated. When
low, the device internally activates the SCK signal. A falling edge on /CS must occur
prior to every op-code.
Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on
the rising edge and outputs occur on the falling edge. Since the device is static, the
clock frequency may be any value between 0 and 20 MHz and may be interrupted at
any time.
Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation
for another task. When /HOLD is low, the current operation is suspended. The device
ignores any transition on SCK or /CS. All transitions on /HOLD must occur while
SCK is low.
Write Protect: This active low pin prevents write operations to the Status Register.
This is critical since other write protection features are controlled through the Status
Register. A complete explanation of write protection is provided below. *Note that the
function of /WP is different from the FM25040 where it prevents all writes to the part.
Serial Input: All data is input to the device on this pin. The pin is sampled on the
rising edge of SCK and is ignored at other times. It should always be driven to a valid
logic level to meet IDD specifications.
* SI may be connected to SO for a single pin data interface.
Serial Output: This is the data output pin. It is driven during a read and remains tri-
stated at all other times including when /HOLD is low. Data transitions are driven on
the falling edge of the serial clock.
* SO may be connected to SI for a single pin data interface.
Power Supply (2.7V to 3.65V)
Ground
Instruction Register
Instruction Decode
Address Register
Clock Generator
Control Logic
Write Protect
Counter
Figure 1. Block Diagram
13
Nonvolatile Status
Data I/O Register
FRAM Array
2,048 x 32
Register
3
8
FM25CL64
SO
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