PIC16F684-E/ML Microchip Technology, PIC16F684-E/ML Datasheet - Page 110
PIC16F684-E/ML
Manufacturer Part Number
PIC16F684-E/ML
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,16PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F684-ISL.pdf
(4 pages)
4.PIC16F684-ISL.pdf
(192 pages)
5.PIC16F684-ISL.pdf
(6 pages)
Specifications of PIC16F684-E/ML
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
16-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT16QFN1 - SOCKET TRANSITION 14DIP TO 16QFN
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F684-ISL PDF datasheet #3
- PIC16F684-ISL PDF datasheet #4
- PIC16F684-ISL PDF datasheet #5
- Current page: 110 of 192
- Download datasheet (4Mb)
PIC16F684
FIGURE 12-8:
TABLE 12-6:
DS41202F-page 108
INTCON
IOCA
PIR1
PIE1
Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition.
INSTRUCTION FLOW
Name
GIE bit
(INTCON reg.)
INTF flag
(INTCON reg.)
CLKOUT
INT pin
OSC1
Note 1: INTF flag is sampled here (every Q1).
Instruction
Executed
Instruction
Fetched
PC
2: Asynchronous interrupt latency = 3-4 T
3: CLKOUT is available only in INTOSC and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 15.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
Shaded cells are not used by the interrupt module.
(3)
EEIF
EEIE
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
Bit 7
GIE
—
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Q1
Inst (PC – 1)
Inst (PC)
(1)
INT PIN INTERRUPT TIMING
Q2
ADIE
PEIE
ADIF
Bit 6
PC
—
(4)
Q3 Q4
CCP1IF
CCP1IE
IOCA5
(5)
Bit 5
T0IE
Q1
Inst (PC + 1)
Inst (PC)
IOCA4 IOCA3 IOCA2
INTE
C2IE
Bit 4
C2IF
Q2
(1)
PC + 1
Q3 Q4
CY
. Synchronous latency = 3 T
RAIE
C1IE
Bit 3
C1IF
Interrupt Latency
Q1
OSFIF
OSFIE
Dummy Cycle
Bit 2
T0IF
Q2
PC + 1
—
Q3 Q4
TMR2IF
TMR2IE
IOCA1
INTF
Bit 1
(2)
CY
, where T
Q1
Dummy Cycle
Inst (0004h)
TMR1IF 0000 0000 0000 0000
TMR1IE 0000 0000 0000 0000
IOCA0
Q2
RAIF
Bit 0
0004h
CY
= instruction cycle time. Latency
Q3 Q4
© 2007 Microchip Technology Inc.
0000 0000 0000 0000
--00 0000 --00 0000
POR, BOR
Value on:
Q1
Inst (0005h)
Q2
Inst (0004h)
0005h
Value on
all other
Q3 Q4
Resets
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