PIC16F76-E/SP Microchip Technology, PIC16F76-E/SP Datasheet - Page 662
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PIC16F76-E/SP
Manufacturer Part Number
PIC16F76-E/SP
Description
28 PIN, 14KB STD FLASH, 368 RAM, 22 I/O,
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(6 pages)
4.PIC16F73-ISP.pdf
(174 pages)
5.PIC16F73-ISP.pdf
(14 pages)
6.PIC16F73-ISP.pdf
(12 pages)
Specifications of PIC16F76-E/SP
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC16F76E/SP
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F73-ISP PDF datasheet #4
- PIC16F73-ISP PDF datasheet #5
- PIC16F73-ISP PDF datasheet #6
- Current page: 662 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
Figure A-12:
Table A-3:
DS31034A-page 34-10
D102
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
Parameter
Microchip
No.
100
101
102
103
106
107
109
110
90
91
92
2: A fast-mode I
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
tsu;DAT
LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must out-
put the next data bit to the SDA line
T
the SCL line is released.
SDA
Out
SDA
In
SCL
R
max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I
I
T
T
T
T
T
T
T
T
T
T
T
Cb
2
C Bus Data Timing Specification
HIGH
LOW
R
F
SU
HD
HD
SU
SU
AA
BUF
I
Sym
2
C Bus Data Timing Specification
:
:
:
:
:
STA
STA
DAT
DAT
STO
250 ns must then be met. This will automatically be the case if the device does not stretch the
2
90
C-bus device can be used in a standard-mode I
Clock high time
Clock low time
SDA and SCL
rise time
SDA and SCL fall
time
START condition
setup time
START condition
hold time
Data input hold
time
Data input setup
time
STOP condition
setup time
Output valid from
clock
Bus free time
Bus capacitive loading
103
91
109
Characteristic
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100
106
101
109
0.1Cb
0.1Cb
20 +
20 +
Min
250
100
4.0
0.6
4.7
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.7
1.3
—
—
—
—
—
0
0
107
2
C-bus system, but the requirement
1000
3500
1000
Max
300
300
300
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s
s
s
s
2
C bus specification) before
1997 Microchip Technology Inc.
92
Cb is specified to be from
10 to 400 pF
Cb is specified to be from
10 to 400 pF
Only relevant for repeated
START condition
After this period the first
clock pulse is generated
Note 2
Time the bus must be free
before a new transmis-
sion can start
Note 1
102
Conditions
110
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