PIC16LC774-I/PQ Microchip Technology, PIC16LC774-I/PQ Datasheet
PIC16LC774-I/PQ
Specifications of PIC16LC774-I/PQ
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PIC16LC774-I/PQ Summary of contents
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... A typical @ 3V, 32 kHz - < typical standby current * Enhanced features This is an advanced copy of the data sheet and therefore the contents and specifications are subject to change based on device characterization. 1999 Microchip Technology Inc. PIC16C77X Pin Diagram 600 mil. PDIP, Windowed CERDIP MCLR/V PP ...
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... V SS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RB3/AN9/LVDIN 39 RB2/AN8 38 RB1/SS 37 RB0/INT RD7/PSP7 33 RD6/PSP6 32 RD5/PSP5 31 RD4/PSP4 30 RC7/RX/DT 29 MQFP TQFP RC7/RX/DT 1 RD4/PSP4 2 RD5/PSP5 3 RD6/PSP6 4 RD7/PSP7 PIC16C774 RB0/INT 8 RB1/SS 9 RB2/AN8 10 RB3/AN9/LVDIN 11 Advance Information NC 33 RC0/T1OSO/T1CKI 32 OSC2/CLKOUT 31 OSC1/CLKIN RE2/CS/AN7 27 RE1/WR/AN6 26 RE0/RD/AN5 25 RA5/AN4 24 RA4/T0CKI 23 1999 Microchip Technology Inc. ...
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... Resets (and Delays) Program Memory (14-bit words) Data Memory (bytes) Interrupts I/O Ports Timers Capture/Compare/PWM modules Serial Communications Parallel Communications 12-bit Analog-to-Digital Module Instruction Set 1999 Microchip Technology Inc. PIC16C773 MHz POR, BOR, MCLR, WDT (PWRT, OST) 4K 256 13 Ports A,B MSSP, USART — ...
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... However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please: • Fill out and mail in the reader response form in the back of this data sheet. • E-mail us at webmaster@microchip.com. We appreciate your assistance in making this a better document. DS30275A-page 4 To Our Valued Customers Advance Information 1999 Microchip Technology Inc. ...
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... ADC Timer0 CCP1,2 Note 1: Higher order bits are from the STATUS register. 1999 Microchip Technology Inc. There a two devices (PIC16C773 and PIC16C774) covered by this datasheet. The PIC16C773 devices come in 28-pin packages and the PIC16C774 devices come in 40-pin packages. The 28-pin devices do not have a Parallel Slave Port implemented ...
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... USART Serial Port Advance Information PORTA RA0/AN0 RA1/AN1 RA2/AN2/V -/VRL REF RA3/AN3/V +/VRH REF RA4/T0CKI RA5/AN4 PORTB RB0/INT RB1/SS RB2/AN8 RB3/AN9/LVDIN RB7:RB4 PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTD RD7/PSP7:RD0/PSP0 PORTE RE0/AN5/RD RE1/AN6/WR RE2/AN7/CS 1999 Microchip Technology Inc. ...
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... Note 1: This buffer is a Schmitt Trigger input when configured for the multiplexed function. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 1999 Microchip Technology Inc. Buffer Description ...
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... Interrupt on change pin. 15 I/O TTL Interrupt on change pin. (2) 16 I/O TTL/ST Interrupt on change pin. Serial programming clock. (2) 17 I/O TTL/ST Interrupt on change pin. Serial programming data. I/O = input/output P = power TTL = TTL input ST = Schmitt Trigger input Advance Information 1999 Microchip Technology Inc. ...
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... This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). 4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 1999 Microchip Technology Inc. QFP I/O/P ...
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... PIC16C77X NOTES: DS30275A-page 10 Advance Information 1999 Microchip Technology Inc. ...
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... Interrupt Vector Page 0 On-chip Program Memory Page 1 1999 Microchip Technology Inc. 2.2 Data Memory Organization The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 and RP0 are the bank select bits. ...
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... Bank 3 1999 Microchip Technology Inc. ...
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... These registers can be addressed from any bank. 5: These registers/bits are not implemented on the 28-pin devices read as '0'. 1999 Microchip Technology Inc. The special function registers can be classified into two sets; core (CPU) and peripheral. Those registers asso- ciated with the core functions are described in detail in this section ...
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... TRMT TX9D 0000 -010 0000 -010 0000 0000 0000 0000 — — — — 0000 ---- 0000 ---- LV1 LV0 --00 0101 --00 0101 — — xxxx xxxx uuuu uuuu PCFG1 PCFG0 0000 0000 0000 0000 1999 Microchip Technology Inc. ...
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... Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear. 4: These registers can be addressed from any bank. 5: These registers/bits are not implemented on the 28-pin devices read as '0'. 1999 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 RP0 TO ...
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... Note 1: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. R-1 R/W-x R/W-x R/W Advance Information R = Readable bit W = Writable bit bit0 U = Unimplemented bit, read as ‘0’ Value at POR reset 1999 Microchip Technology Inc. ...
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... TMR0 Rate WDT Rate 000 001 010 011 100 101 110 1 : 128 111 1 : 256 1999 Microchip Technology Inc. Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer. R/W-1 R/W-1 R/W-1 R/W-1 PSA PS2 PS1 PS0 ...
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... R/W-0 R/W-0 R/W-0 R/W-x RBIE T0IF INTF RBIF bit0 Advance Information R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 1999 Microchip Technology Inc. ...
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... TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: PSPIE is reserved on the 28-pin devices, always maintain this bit clear. 1999 Microchip Technology Inc. Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. ...
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... R/W-0 R/W-0 R/W-0 R/W-0 SSPIF CCP1IF TMR2IF TMR1IF bit0 Advance Information R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 1999 Microchip Technology Inc. ...
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... BCLIE: Bus Collision Interrupt Enable bit 1 = Bus Collision interrupt is enabled 0 = Bus Collision interrupt is disabled bit 2-1: Unimplemented: Read as ’0’ bit 0: CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt 1999 Microchip Technology Inc. R/W-0 U-0 U-0 R/W-0 BCLIE — — ...
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... R/W-0 U-0 U-0 R/W-0 BCLIF — — CCP2IF bit0 2 Advance Information R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset C Master was transmitting 1999 Microchip Technology Inc. ...
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... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0: BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) 1999 Microchip Technology Inc. Note: BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent resets to see if BOR is clear, indicating a brown-out has occurred. The BOR status bit is a don’ ...
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... If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto the stack. Therefore, manipulation of the PCLATH<4:3> bits are not required for the return instructions (which POPs the address from the stack). Advance Information 1999 Microchip Technology Inc. ...
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... Direct Addressing from opcode RP1:RP0 6 bank select location select 00h Data Memory(1) 7Fh Bank 0 Note 1: For register file map detail see 1999 Microchip Technology Inc. EXAMPLE 2-1: movlw movwf NEXT clrf incf btfss goto 2-1. CONTINUE : An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS< ...
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... PIC16C77X NOTES: DS30275A-page 26 Advance Information 1999 Microchip Technology Inc. ...
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... STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs ; TRISA<7:6> are always ; read as ’0’. 1999 Microchip Technology Inc. FIGURE 3-1: BLOCK DIAGRAM OF RA3:RA2 PINS Data bus D WR Port Manual, CK Data Latch D ...
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... I/O pin N Data Latch Schmitt CK Q Trigger input buffer RD TRIS only input or internal reference REF + input or output of internal REF Value on: Value on all Bit 0 POR, other resets BOR RA0 --0x 0000 --0u 0000 --11 1111 --11 1111 PCFG0 0000 0000 0000 0000 1999 Microchip Technology Inc. ...
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... Buffer Note 1: I/O pins have diode protection to V and enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>). 1999 Microchip Technology Inc. The RB1 pin is multiplexed with the SSP module slave select (RB1/SS). FIGURE 3-5: (2) RBPU ...
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... To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>). Advance Information BLOCK DIAGRAM OF RB7:RB4 PINS V DD weak P pull-up Data Latch D Q I/O (1) CK pin TRIS Latch D Q TTL CK Input Buffer ST Buffer RD TRIS Latch Port Port EN Q3 and 1999 Microchip Technology Inc. ...
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... OPTION_REG RBPU INTEDG 9Fh ADCON1 ADFM VCFG2 Legend unknown unchanged. Shaded cells are not used by PORTB. 1999 Microchip Technology Inc. Function Input/output pin or external interrupt input. Internal software programmable weak pull-up. Input/output pin or SSP slave select. Internal software programmable weak pull-up. ...
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... TRIS Latch RD TRIS Peripheral ( PORT Peripheral input Note 1: I/O pins have diode protection Port/Peripheral select signal selects between port data and peripheral output. 3: Peripheral OE (output enable) is only activated if peripheral select is active. Advance Information ( I/O (1) pin Schmitt Trigger and 1999 Microchip Technology Inc. ...
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... RC7 RC6 87h TRISC PORTC Data Direction Register Legend unknown unchanged. 1999 Microchip Technology Inc. Function Input/output port pin or Timer1 oscillator output/Timer1 clock input Input/output port pin or Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output Input/output port pin or Capture1 input/Compare1 output/PWM1 output RC3 can also be the synchronous serial clock for both SPI and I modes ...
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... PORTE Data Direction Bits Advance Information I/O PORT MODE) Q (1) I/O pin Q Schmitt Trigger input buffer RD TRIS and Value on: Value on all Bit 0 POR, other resets BOR RD0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 0000 -111 0000 -111 1999 Microchip Technology Inc. ...
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... Bit2: Direction Control bit for pin RE2/CS/AN7 1 = Input 0 = Output bit 1: Bit1: Direction Control bit for pin RE1/WR/AN6 1 = Input 0 = Output bit 0: Bit0: Direction Control bit for pin RE0/RD/AN5 1 = Input 0 = Output 1999 Microchip Technology Inc. FIGURE 3-11: PORTE BLOCK DIAGRAM (IN I/O PORT MODE) Data bus D WR PORT CK Data Latch D ...
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... Bit 1 — — RE2 RE1 PSPMODE — PORTE Data Direction Bits VCFG0 PCFG3 PCFG2 PCFG1 Advance Information Value on: Value on all Bit 0 POR, other resets BOR RE0 ---- -xxx ---- -uuu 0000 -111 0000 -111 PCFG0 0000 0000 0000 0000 1999 Microchip Technology Inc. ...
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... A read from the PSP occurs when both the CS and RD lines are first detected low. FIGURE 3-14: PARALLEL SLAVE PORT WRITE WAVEFORMS PORTD<7:0> IBF OBF PSPIF 1999 Microchip Technology Inc. FIGURE 3-13: PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) Data bus D WR PORT PORT ...
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... SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 VCFG0 PCFG3 PCFG2 PCFG1 Advance Information Value on: Value on all Bit 0 POR, other resets BOR xxxx xxxx uuuu uuuu RE0 ---- -xxx ---- -uuu 0000 -111 0000 -111 0000 0000 0000 0000 PCFG0 0000 0000 0000 0000 1999 Microchip Technology Inc. ...
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... RA4/T0CKI pin T0SE T0CS Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>). 2: The prescaler is shared with Watchdog Timer (refer to 1999 Microchip Technology Inc. Additional information on external clock requirements is available in the PICmicro™ Mid-Range Reference Manual, (DS33023). 4.2 Prescaler An 8-bit counter is available as a prescaler for the ...
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... PORTA Data Direction Register Advance Information Data Bus 8 TMR0 reg Set flag bit T0IF on Overflow Value on: Value on all Bit 0 POR, other resets BOR xxxx xxxx uuuu uuuu RBIF 0000 000x 0000 000u PS0 1111 1111 1111 1111 --11 1111 --11 1111 1999 Microchip Technology Inc. ...
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... External clock from pin RC0/T1OSO/T1CKI (on the rising edge Internal clock (F /4) OSC bit 0: TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 1999 Microchip Technology Inc. 5.1 Timer1 Operation Timer1 can operate in one of these modes: • timer • synchronous counter • asynchronous counter The operating mode is determined by the clock select bit, TMR1CS (T1CON< ...
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... Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. DS30275A-page 42 0 TMR1L 1 TMR1ON T1SYNC on/off 1 Prescaler T1OSCEN F /4 OSC Enable Internal 0 (1) Oscillator Clock 2 T1CKPS1:T1CKPS0 TMR1CS Advance Information Synchronized clock input Synchronize det SLEEP input 1999 Microchip Technology Inc. ...
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... Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by the Timer1 module. Note 1: These bits are reserved on the 28-pin devices, always maintain these bits clear. 1999 Microchip Technology Inc. 5.3 Timer1 Interrupt The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit TMR1IF (PIR1< ...
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... PIC16C77X NOTES: DS30275A-page 44 Advance Information 1999 Microchip Technology Inc. ...
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... Timer2 is off bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 1999 Microchip Technology Inc. 6.1 Timer2 Operation Timer2 can be used as the PWM time-base for PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device reset. ...
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... Comparator EQ PR2 reg Value on: Value on Bit 0 POR, all other BOR resets 0000 000x 0000 000u RBIF 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 1111 1111 1111 1111 1999 Microchip Technology Inc. ...
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... Compare mode, trigger special event (CCPxIF bit is set; CCP1 resets TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module is enabled)) 11xx = PWM mode 1999 Microchip Technology Inc. CCP2 Module Capture/Compare/PWM Register2 (CCPR2) is com- prised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte) ...
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... MOVLW NEW_CAPT_PS MOVWF CCP1CON CCPR1L TMR1L Advance Information Example 7-1 shows the recom- CHANGING BETWEEN CAPTURE PRESCALERS ;Turn CCP module off ;Load the W reg with ; the new prescaler ; mode value and CCP ON ;Load CCP1CON with this ; value 1999 Microchip Technology Inc. ...
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... Shaded cells are not used by Capture and Timer1. Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin, always maintain these bits clear. 1999 Microchip Technology Inc. 7.2.1 CCP PIN CONFIGURATION The user must configure the RC2/CCP1 pin as an out- put by clearing the TRISC< ...
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... For an example PWM period and duty cycle calcu- lation, see the PICmicro™ Mid-Range Reference Manual, (DS33023). Advance Information • OSC (TMR2 prescale value) Section 6.0) is Tosc • (TMR2 prescale value OSC log F PWM bits log(2) 1999 Microchip Technology Inc. ...
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... Shaded cells are not used by PWM and Timer2. Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin, always maintain these bits clear. 1999 Microchip Technology Inc. 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 16 ...
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... PIC16C77X NOTES: DS30275A-page 52 Advance Information 1999 Microchip Technology Inc. ...
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... These peripheral devices may be serial EEPROMs, shift registers, dis- play drivers, A/D converters, etc. The MSSP module can operate in one of two modes: • Serial Peripheral Interface (SPI) 2 • Inter-Integrated Circuit (I C™) 1999 Microchip Technology Inc. Advance Information PIC16C77X DS30275A-page 53 ...
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... Data Transmit complete (does not include the ACK and stop bits), SSPBUF is empty DS30275A-page 54 R-0 R-0 R-0 R bit0 (Figure 8-6, Figure 8-8, and Figure 8- mode only mode only) Advance Information R =Readable bit W =Writable bit U =Unimplemented bit, read as ‘0’ =Value at POR reset 1999 Microchip Technology Inc. ...
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... SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin 2 0110 = I C slave mode, 7-bit address 2 0111 = I C slave mode, 10-bit address 2 1000 = I C master mode, clock = F 1xx1 = Reserved 1x1x = Reserved 1999 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 R/W-0 SSPM3 SSPM2 SSPM1 SSPM0 bit0 2 C conditions were not valid for a ...
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... C master mode only master mode only master mode only master mode only master mode only module is not in the idle mode, this bit may not be Advance Information R =Readable bit W =Writable bit U =Unimplemented bit, Read as ‘0’ =Value at POR reset 1999 Microchip Technology Inc. ...
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... SCK) • Clock Rate (Master mode only) • Slave Select Mode (Slave mode only) Figure 8-4 shows the block diagram of the MSSP mod- ule when in SPI mode. 1999 Microchip Technology Inc. FIGURE 8-4: MSSP BLOCK DIAGRAM (SPI MODE) Read SDI ...
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... Master sends data — Slave sends data • Master sends dummy data — Slave sends data SPI Slave SSPM3:SSPM0 = 010xb SDO SDI SDI SDO LSb MSb Serial Clock SCK SCK Advance Information Serial Input Buffer (SSPBUF) Shift Register (SSPSR) LSb PROCESSOR 2 1999 Microchip Technology Inc. ...
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... Input Sample (SMP = 0) SDI (SMP = 1) bit7 Input Sample (SMP = 1) SSPIF SSPSR to SSPBUF 1999 Microchip Technology Inc. Figure 8-6, Figure 8-8, and is transmitted first. In master mode, the SPI clock rate (bit rate) is user programmable to be one of the follow- ing: • ( OSC CY • ...
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... SDO pin can be configured as an input. This disables transmissions from the SDO. The SDI can always be left as an input (SDI function) since it cannot create a bus conflict. bit6 bit7 bit7 Advance Information . DD bit0 bit0 Next Q4 cycle after Q2 1999 Microchip Technology Inc. ...
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... SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit7 SDI (SMP = 0) bit7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF 1999 Microchip Technology Inc. bit6 bit5 bit4 bit2 bit3 bit6 bit2 bit5 bit4 bit3 Advance Information PIC16C77X bit1 bit0 bit0 Next Q4 cycle after Q2 ...
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... P S R/W UA Advance Information Bit 0 POR, BOR MCLR, WDT RBIF 0000 000x 0000 000u TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 xxxx xxxx uuuu uuuu SSPM0 0000 0000 0000 0000 BF 0000 0000 0000 0000 1999 Microchip Technology Inc. ...
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... SSPSR reg SDA MSb LSb Match detect SSPADD reg Start and Stop bit detect 1999 Microchip Technology Inc. FIGURE 8-11: I SSPADD<6:0> 7 Baud Rate Generator SCL SDA Internal data bus Two pins are used for data transfer. These are the SCL pin, which is the clock, and the SDA pin, which is the data ...
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... SSPIF. Note: Following the Repeated Start condition (step 7) in 10-bit mode, the user only needs to match the first 7-bit address. The and user does not update the SSPADD for the second half of the address. Advance Information 1999 Microchip Technology Inc. ...
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... SCL S SSPIF BF (SSPSTAT<0>) SSPOV (SSPCON<6>) 1999 Microchip Technology Inc. An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft- ware. The SSPSTAT register is used to determine the status of the received byte. Note: The SSPBUF will be loaded if the SSPOV bit is set and the BF flag is cleared ...
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... SCL held low while CPU responds to SSPIF cleared in software SSPBUF is written in software Set bit after writing to SSPBUF (the SSPBUF must be written-to before the CKP bit can be set) Advance Information R Transmitting Data Not ACK From SSP interrupt service routine 1999 Microchip Technology Inc. ...
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... I FIGURE 8-14: C SLAVE-TRANSMITTER (10-BIT ADDRESS) 1999 Microchip Technology Inc. Advance Information PIC16C77X DS30275A-page 67 ...
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... PIC16C77X 2 FIGURE 8-15 SLAVE-RECEIVER (10-BIT ADDRESS) DS30275A-page 68 Advance Information 1999 Microchip Technology Inc. ...
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... SSPOV (SSPCON<6>) GCEN (SSPCON2<7>) 1999 Microchip Technology Inc. If the general call address matches, the SSPSR is transfered to the SSPBUF, the BF flag is set (eighth bit), and on the falling edge of the ninth bit (ACK bit) the SSPIF flag is set. When the interrupt is serviced. The source for the ...
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... TMR1IE 0000 0000 0000 0000 CCP2IF 0--- 0--0 0--- 0--0 CCP2IE 0--- 0--0 0--- 0--0 xxxx xxxx uuuu uuuu SSPM0 0000 0000 0000 0000 SEN 0000 0000 0000 0000 BF 0000 0000 0000 0000 2 C mode. 1999 Microchip Technology Inc. ...
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... FIGURE 8-17: SSP BLOCK DIAGRAM (I SDA SDA in SCL SCL in Bus Collision 1999 Microchip Technology Inc. In master mode, the SCL and SDA lines are manipu- lated by the MSSP hardware. The following events will cause SSP Interrupt Flag bit, SSPIF set (SSP Interrupt if enabled): • START condition • ...
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... The module generates an interrupt at the end of the ninth clock cycle by setting SSPIF. g) The user loads the SSPBUF with eight bits of data. h) DATA is shifted out the SDA pin until all 8 bits are transmitted. Advance Information operation. The baud 1999 Microchip Technology Inc. ...
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... SCL de-asserted but slave holds SCL low (clock arbitration) SCL BRG 03h value BRG reload 1999 Microchip Technology Inc master mode, the BRG is reloaded automatically. If Clock Arbitration is taking place for instance, the BRG will be reloaded when the SCL pin is sampled high (Figure 8-19). ...
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... SSPCON2 is disabled until the START condition is complete. ), the BRG Set S bit (SSPSTAT<3>) SDA = 1, At completion of start bit, SCL = 1 Hardware clears SEN bit and sets SSPIF bit T T Write to SSPBUF occurs here BRG BRG 1st Bit T BRG T BRG S Advance Information 2nd Bit 1999 Microchip Technology Inc. ...
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... FIGURE 8-21: START CONDITION FLOWCHART Bus collision detected, Set BCLIF, Release SCL, Clear SEN No Yes No SCL SCL = 0? Reset BRG 1999 Microchip Technology Inc. SSPEN = 1, SSPCON<3:0> = 1000 Idle Mode SEN (SSPCON2<0> SDA = 1? SCL = 1? Yes Load BRG with SSPADD<6:0> No BRG SDA = 0? Rollover? Yes ...
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... SSPCON2 is disabled until the Repeated Start condition is complete. Set S (SSPSTAT<3>) SDA = 1, At completion of start bit, SCL = 1 hardware clear RSEN bit and set SSPIF BRG BRG BRG Write to SSPBUF occurs here. T BRG Sr = Repeated Start Advance Information 1st Bit T BRG 1999 Microchip Technology Inc. ...
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... FIGURE 8-23: REPEATED START CONDITION FLOWCHART (PAGE 1) B Bus Collision, Set BCLIF, Release SDA, Clear RSEN 1999 Microchip Technology Inc. Start Idle Mode, SSPEN = 1, SSPCON<3:0> = 1000 RSEN = 1 Force SCL = 0 No SCL = 0? Yes Release SDA, Load BRG with SSPADD<6:0> No BRG rollover? Yes ...
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... No No SDA = 0? SCL = 1? Yes Reset BRG Force SDA = 0, Load BRG with SSPADD<6:0> SCL = ’0’? Yes Force SCL = 0, Reset BRG Repeated Start condition done, Advance Information A BRG rollover? Yes Set S BRG rollover? Yes Clear RSEN, Set SSPIF. 1999 Microchip Technology Inc. ...
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... SSPIF is set, the BF flag is cleared, and the baud rate generator is turned off until another write to the SSPBUF takes place, holding SCL low and allowing SDA to float. 1999 Microchip Technology Inc. 8.2.11.7 BF STATUS FLAG In transmit mode, the BF bit (SSPSTAT<0>) is set when the CPU writes to SSPBUF and is cleared when all 8 bits are shifted out ...
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... Load BRG with SSPADD<6:0>, start BRG count No BRG rollover? Yes Force SCL = 1, Stop BRG No SCL = 1? Yes Read SDA and place into AKSTAT bit (SSPCON2<6>) Load BRG with SSPADD<6:0>, count high time No Rollover? Yes Force SCL = 0, Set SSPIF 1999 Microchip Technology Inc. ...
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... FIGURE 8-26 MASTER MODE TIMING (TRANSMISSION 10-BIT ADDRESS) 1999 Microchip Technology Inc. Advance Information PIC16C77X DS30275A-page 81 ...
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... WCOL STATUS FLAG If the user writes the SSPBUF when a receive is already in progress (i.e. SSPSR is still shifting in a data byte), then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). Advance Information 1999 Microchip Technology Inc. ...
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... FIGURE 8-27: MASTER RECEIVER FLOWCHART No Move contents of SSPSR 1999 Microchip Technology Inc. Idle mode RCEN = 1 Num_Clocks = 0, Release SDA Force SCL=0, Load BRG w/ SSPADD<6:0>, start count BRG No rollover? Yes Release SCL (Clock Arbitration) No SCL = 1? Yes Sample SDA, Shift data into SSPSR Load BRG with SSPADD< ...
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... PIC16C77X 2 FIGURE 8-28 MASTER MODE TIMING (RECEPTION 7-BIT ADDRESS) DS30275A-page 84 Advance Information 1999 Microchip Technology Inc. ...
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... SSPIF Set SSPIF at the end of receive Note one baud rate generator period. BRG 1999 Microchip Technology Inc. rate generator counts for T pulled low. Following this, the AKEN bit is automati- cally cleared, the baud rate generator is turned off, and bit, AKEN the SSP module then goes into IDLE mode. ...
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... Load BRG with SSPADD <6:0>, start count. DS30275A-page 86 BRG Yes rollover? No Yes SCL = 0? Reset BRG No No AKDT = 1? Yes Yes SDA = 1? No Bus collision detected, Set BCLIF, Release SCL, Clear AKEN Advance Information Force SCL = 0, Clear AKEN, Set SSPIF 1999 Microchip Technology Inc. ...
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... SDA SDA asserted low before rising edge of clock to setup stop condition. Note one baud rate generator period. BRG 1999 Microchip Technology Inc. while SCL is high, the P bit (SSPSTAT<4>) is set later the PEN bit is cleared and the SSPIF bit is BRG set (Figure 8-31) ...
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... DS30275A-page 88 Start BRG No BRG rollover? Yes Release SDA, Start BRG No BRG rollover? Yes Bus Collision detected, No Set BCLIF, P bit Set? Clear PEN Yes SDA going from while SCL = 1 Set SSPIF, Stop Condition done PEN cleared. Advance Information 1999 Microchip Technology Inc. ...
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... Release SCL, Slave device holds SCL low. SCL SDA T BRG 1999 Microchip Technology Inc. 8.2.16 SLEEP OPERATION While in sleep mode, the I addresses or data, and when an address match or complete byte transfer occurs wake the processor from sleep ( if the SSP interrupt is enabled). ...
Page 90
... S and P bits are cleared. Sample SDA. While SCL is high SDA line pulled low by another source data doesn’t match what is driven by the master. Bus collision has occurred. SDA released by master Advance Information 2 C bus Set bus collision interrupt. 1999 Microchip Technology Inc. ...
Page 91
... S bit and SSPIF set because BCLIF SDA = 0, SCL = 1 S SSPIF 1999 Microchip Technology Inc. while SDA is high, a bus collision occurs, because it is assumed that another master is attempting to drive a data ’1’ during the START condition. If the SDA pin is sampled low during this count, the ...
Page 92
... Bus collision occurs, Set BCLIF. SDA = 0, SCL = 1 Set S Set SSPIF BRG T BRG S SCL pulled low after BRG Timeout Set SEN, enable start sequence if SDA = 1, SCL = 1 SDA = 0, SCL = 1 Set SSPIF Advance Information Interrupts cleared in software. ’0’ ’0’ Interrupts cleared in software. 1999 Microchip Technology Inc. ...
Page 93
... RSEN ’0’ S ’0’ SSPIF 1999 Microchip Technology Inc. however SDA is sampled high then the BRG is reloaded and begins counting. If SDA goes from high to low before the BRG times out, no bus collision occurs, because no two masters can assert SDA at exactly the same time. ...
Page 94
... This is another case of another master attempting to drive a data ’0’ (Figure T BRG BRG T T BRG SCL goes low before SDA goes high Set BCLIF Advance Information 8-40). SDA sampled T BRG low after T , BRG Set BCLIF ’0’ ’0’ BRG 1999 Microchip Technology Inc. ...
Page 95
... For OL FIGURE 8-42: SAMPLE DEVICE CONFIGURATION FOR I R SDA SCL NOTE devices with input levels related to V line to which the pull up resistor is also connected. 1999 Microchip Technology Inc example, with a supply voltage max = 0. mA 1.7 k ...
Page 96
... PIC16C77X NOTES: DS30275A-page 96 Advance Information 1999 Microchip Technology Inc. ...
Page 97
... TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0: TX9D: 9th bit of transmit data. Can be parity bit. 1999 Microchip Technology Inc. The USART can be configured in the following modes: • Asynchronous (full duplex) • Synchronous - Master (half duplex) • Synchronous - Slave (half duplex) Bit SPEN (RCSTA< ...
Page 98
... Overrun error (Can be cleared by clearing bit CREN overrun error bit 0: RX9D: 9th bit of received data (Can be parity bit) DS30275A-page 98 R/W-0 R-0 R-0 R-x ADDEN FERR OERR RX9D bit0 Advance Information R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ =Value at POR reset 1999 Microchip Technology Inc. ...
Page 99
... RCSTA SPEN RX9 SREN CREN ADDEN 99h SPBRG Baud Rate Generator Register Legend unknown unimplemented read as '0'. Shaded cells are not used by the BRG. 1999 Microchip Technology Inc. EXAMPLE 9-1: Desired Baud rate = Fosc / ( 1)) 9600 = X = Calculated Baud Rate=16000000 / (64 (25 + 1)) = ...
Page 100
... MHz SPBRG % value KBAUD ERROR (decimal 1.203 +0.23 92 2.380 -0.83 46 9.322 -2.90 11 18.64 -2. 111 0.437 - 255 32.768 kHz SPBRG SPBRG % value % value ERROR (decimal) KBAUD ERROR (decimal) +0.16 51 0.256 -14.67 1 +0. -6. 0.512 - 0 - 255 0.0020 - 255 1999 Microchip Technology Inc. ...
Page 101
... 625 1250 1999 Microchip Technology Inc. 10 MHz SPBRG SPBRG % value % value ERROR (decimal) KBAUD ERROR (decimal) +0.16 103 9.615 +0.16 64 +0.16 51 18.939 -1.36 32 +0.16 25 39.062 +1.7 15 +2.12 16 56.818 -1 ...
Page 102
... TX9D. 7. Load data to the TXREG register (starts trans- mission). Data Bus TXREG register 8 MSb LSb (8) 0 TSR register TRMT TX9 TX9D Advance Information ), the TXREG register is empty and CY (Section 9.1) Pin Buffer and Control RC6/TX/CK pin SPEN 1999 Microchip Technology Inc. ...
Page 103
... SPBRG Baud Rate Generator Register Legend unknown unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission. Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear. 1999 Microchip Technology Inc. Bit 0 Bit 1 WORD 1 ...
Page 104
... If any error occurred, clear the error by clearing enable bit CREN. • If the device has been addressed, clear the ADDEN bit to allow data bytes and address bytes to be read into the receive buffer, and interrupt the CPU. Figure 9-6. Advance Information 1999 Microchip Technology Inc. ...
Page 105
... Load RSR Bit8 = 0, Data Byte Read RCIF Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (receive buffer) because ADDEN = 1. 1999 Microchip Technology Inc. OERR CREN 64 RSR register MSb or 16 ...
Page 106
... Advance Information WORD 1 RCREG Value on: Value on Bit 0 POR, all other BOR Resets 0000 0000 0000 0000 RX9D 0000 000x 0000 000x 0000 0000 0000 0000 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 1999 Microchip Technology Inc. ...
Page 107
... Legend unknown unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission. Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear. 1999 Microchip Technology Inc. enabled/disabled by setting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in soft- ware ...
Page 108
... TXIF bit TRMT bit TXEN bit DS30275A-page 108 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4 Bit 1 Bit 2 Bit 7 Bit 0 WORD 1 bit0 bit2 bit1 Advance Information Bit 1 Bit 7 WORD 2 ’1’ bit6 bit7 1999 Microchip Technology Inc. ...
Page 109
... CREN bit RCIF bit (interrupt) Read RXREG Note: Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRGH = '0'. 1999 Microchip Technology Inc. 3. Ensure bits CREN and SREN are clear interrupts are desired, then set enable bit RCIE 9-bit reception is desired, then set bit RX9. ...
Page 110
... RCIE was set. 6. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 7. Read the 8-bit received data by reading the RCREG register any error occurred, clear the error by clearing bit CREN. Advance Information 1999 Microchip Technology Inc. ...
Page 111
... SPBRG Baud Rate Generator Register Legend unknown unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception. Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear. 1999 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 ...
Page 112
... PIC16C77X NOTES: DS30275A-page 112 Advance Information 1999 Microchip Technology Inc. ...
Page 113
... Note 1: These are the minimum trip points for the LVD, see Table 15-3 for the trip point tolerances. Selection of an unused setting may result in an inadvertant interrupt. 1999 Microchip Technology Inc. The source for the reference voltages comes from the bandgap reference circuit. The bandgap circuit is ener- ...
Page 114
... BGST bit in the LVDCON register. The voltage references will not be reliable until the bandgap is stable as shown by BGST being set. Advance Information U-0 — Readable bit W = Writable bit bit0 U = Unimplemented bit, read as ‘0’ =Value at POR reset 1999 Microchip Technology Inc. ...
Page 115
... Once the LV bits have been programmed for the speci- fied trip voltage, the low-voltage detect circuitry is then enabled by setting the LVDEN (LVDCON<4>) bit. 1999 Microchip Technology Inc. control. This allows a user to power the module on and off to periodically monitor the supply voltage, and thus minimize total current consumption ...
Page 116
... PIC16C77X NOTES: DS30275A-page 116 Advance Information 1999 Microchip Technology Inc. ...
Page 117
... A/D conversion completed/not in progress bit 0: ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter is shutoff and consumes no operating current 1999 Microchip Technology Inc. The A/D module has four registers. These registers are: • A/D Result Register Low ADRESL • A/D Result Register High ADRESH • ...
Page 118
... PCFG3 PCFG2 PCFG1 PCFG0 bit 0 A REF A VSS - REF Internal VRL A VSS A VSS - REF Internal VRL A VSS (1) AN5 AN4 AN3 AN2 AN1 AN0 Advance Information R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 1999 Microchip Technology Inc. ...
Page 119
... A/D port configuration bits (PCFG3:PCFG0). 1999 Microchip Technology Inc. After the A/D module has been configured as desired. and the analog input channels have their correspond- ing TRIS bits selected for port inputs, the selected channel must be acquired before conversion is started ...
Page 120
... A/D VCFG2:VCFG0 Converter V REFL (Reference voltage) VCFG2:VCFG0 DS30275A-page 120 CHS3:CHS0 AV DD VRH VRL VRL AV SS Note 1: Not available on 28-pin devices. Advance Information RB3/AN9 RB2/AN8 (1) RE2/AN7 (1) RE1/AN6 (1) RE0/AN5 (1) RA5/AN4 RA3/AN3/V +/VRH REF RA2/AN2/V -/VRL REF RA1/AN1 RA0/AN0 1999 Microchip Technology Inc. ...
Page 121
... A/D Conversion : ;The ADIF bit will be ;set and the GO/DONE bit : ;cleared upon completion- ;of the A/D conversion. 1999 Microchip Technology Inc. Note that these options are the same as those of the 8-bit A/ for set- AD For correct A/D conversions, the A/D conversion clock ...
Page 122
... Abort Conversion SLEEP Instruction? ADIF = 0 No Finish Conversion SLEEP Power down A ADIF = 1 Wait DS30275A-page 122 Yes Finish Conversion SLEEP Instruction ADIF = 1 No Wake-up Finish Conversion From Sleep ADIF = 1 No Stay in Sleep Wait Powerdown A/D Advance Information Yes Wait 1999 Microchip Technology Inc. ...
Page 123
... After a conversion has completed time must be waited before sampling can begin again. During this time the holding capacitor is not connected to the selected A/D input channel. 1999 Microchip Technology Inc. source impedance (R switch (R ) impedance directly affect the time SS required to charge the capacitor C ...
Page 124
... Legend C = input capacitance PIN V = threshold voltage leakage current at the pin due to LEAKAGE various junctions R = interconnect resistance sampling switch C = sample/hold capacitance (from DAC) HOLD DS30275A-page 124 † Sampling Switch LEAKAGE V = 0.6V T 100 Advance Information HOLD Sampling Switch ( k ) 1999 Microchip Technology Inc. ...
Page 125
... The value that is in the ADRESH and ADRESL registers are not modified. The ADRESH and ADRESL registers will contain unknown data after a Power-on Reset. 1999 Microchip Technology Inc. 11.9 Faster Conversion - Lower Resolution Trade-off Not all applications require a result with 12-bits of res- olution, but may instead require a faster conversion time ...
Page 126
... CHS3 ADON 0000 0000 0000 0000 PCFG1 PCFG0 0000 0000 0000 0000 --0x 0000 --0u 0000 xxxx 11xx uuuu 11uu RE1 RE0 ---- -000 ---- -000 --11 1111 --11 1111 1111 1111 1111 1111 0000 -111 0000 -111 1999 Microchip Technology Inc. ...
Page 127
... Microchip Technology Inc. Some of the core features provided may not be neces- sary to each application that a device may be used for. The configuration word bits allow these features to be features configured/enabled/disabled as necessary ...
Page 128
... A difference from the other mid-range devices may be noted in that the device can be driven from an external clock only when configured in HS mode Advance Information FOSC0 Register: CONFIG Address 2007h 1 bit0 oscillation (Figure 12-2). The (Figure 12-3). 1999 Microchip Technology Inc. ...
Page 129
... Panasonic EFO-A455K04B 2.0 MHz Murata Erie CSA2.00MG 4.0 MHz Murata Erie CSA4.00MG 8.0 MHz Murata Erie CSA8.00MT 16.0 MHz Murata Erie CSA16.00MX All resonators used did not have built-in capacitors. 1999 Microchip Technology Inc. TABLE 12-2 Osc Type LP To internal XT logic SLEEP ...
Page 130
... R and C components used need to be taken into account for each application. shows how the R/C combination is connected to the PIC16C77X. FIGURE 12-4: RC OSCILLATOR MODE V DD Rext OSC1 Cext V SS OSC2/CLKOUT Fosc/4 DS30275A-page 130 Figure 12-4 Internal clock PIC16C77X Advance Information 1999 Microchip Technology Inc. ...
Page 131
... Ripple counter RC OSC Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. 1999 Microchip Technology Inc. Some registers are not affected in any reset condition. Their status is unknown on a power-up reset and unchanged in any other reset. Most other registers are ...
Page 132
... PWRT configuration word bit should be cleared (enabled) when brown-out is enabled. Advance Information rises above BOR trippoint falls below the specified trippoint for falls below the trippoint for DD rises above BV . The Power- drops below DD rises above DD 1999 Microchip Technology Inc. ...
Page 133
... Legend unchanged unknown unimplemented bit read as '0'. Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 1999 Microchip Technology Inc. Table 12-5 shows the reset conditions for some special function registers, while conditions for all the registers ...
Page 134
... Microchip Technology Inc. ...
Page 135
... FIGURE 12-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 1999 Microchip Technology Inc. MCLR Resets Wake-up via WDT or WDT Reset ---1 1111 --11 1111 1111 1111 1111 1111 1111 1111 ...
Page 136
... PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 12-10: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS30275A-page 136 T PWRT T T PWRT PWRT T OST Advance Information ): CASE 1 DD OST ): CASE 2 DD OST 1999 Microchip Technology Inc. ...
Page 137
... PIC16C774 Yes Yes Yes Yes 1999 Microchip Technology Inc. The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. The peripheral interrupt flags are contained in the spe- cial function registers PIR1 and PIR2. The correspond- ...
Page 138
... The example: a) Stores the W register. b) Stores the STATUS register in bank 0. c) Stores the PCLATH register. d) Executes the interrupt service routine code (User-generated). e) Restores the STATUS register (and bank select bit). f) Restores the W and PCLATH registers. Advance Information 1999 Microchip Technology Inc. ...
Page 139
... Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Figure 12-1 for the full description of the configuration word bits. 1999 Microchip Technology Inc. The WDT can be permanently disabled by clearing configuration bit WDTE WDT time-out period values may be found in the Elec- trical Specifications section under parameter #31 ...
Page 140
... SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruc- tion should be executed before a SLEEP instruction. 2 C). Advance Information 1999 Microchip Technology Inc. ...
Page 141
... It is recom- mended that only the 4 least significant bits of the ID location are used. For ROM devices, these values are submitted along with the ROM code. 1999 Microchip Technology Inc (2) OST ...
Page 142
... PIC16C77X NOTES: DS30275A-page 142 Advance Information 1999 Microchip Technology Inc. ...
Page 143
... Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time conditional test is true or the program counter is changed as a result of an instruc- tion, the instruction execution time 1999 Microchip Technology Inc. Table 13-2 lists the instructions recognized by the MPASM assembler. Figure 13-1 shows the general formats that the instruc- tions can have ...
Page 144
... C,DC,Z kkkk kkkk Z kkkk kkkk kkkk kkkk TO PD 0110 0100 , kkkk kkkk Z kkkk kkkk kkkk kkkk 0000 1001 kkkk kkkk 0000 1000 0110 0011 C,DC,Z kkkk kkkk Z kkkk kkkk 1999 Microchip Technology Inc. ...
Page 145
... Both systems will operate across the entire operating speed reange of the PICmicro MCU. 1999 Microchip Technology Inc. 14.3 ICEPIC: Low-Cost PICmicro In-Circuit Emulator ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC12CXXX, PIC16C5X and PIC16CXXX families of 8-bit OTP microcontrollers ...
Page 146
... The PICDEM-3 provides an addi- tional RS-232 interface and Windows 3.1 software for showing the demultiplexed LCD signals on a PC. A sim- ple serial interface allows the user to construct a hard- ware demultiplexer for the LCD signals. 1999 Microchip Technology Inc. ...
Page 147
... MPASM provides a rich directive language to support programming of the PICmicro. Directives are helpful in making the development of your assemble source code shorter and more maintainable. 1999 Microchip Technology Inc. PIC16C77X 14.12 Software Simulator (MPLAB-SIM) The MPLAB-SIM Software Simulator allows code development host environment ...
Page 148
... Programming Tools K L evaluation and programming tools support EE OQ Microchips HCS Secure Data Products. The HCS eval- uation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters. DS30275A-page 148 1999 Microchip Technology Inc. ...
Page 149
... Products Emulator Tools 1999 Microchip Technology Inc. á á á á á á á á á á á á á á á á á á ...
Page 150
... PIC16C77X NOTES: DS30275A-page 150 1999 Microchip Technology Inc. ...
Page 151
... It is recommended that the user select the device type that ensures the specifications required. 1999 Microchip Technology Inc. (except V , MCLR. and RA4).......................................... -0. > PIC16C773-20 PIC16LC773-04 PIC16C774-20 PIC16LC774- 2.5V to 5.5V DD 2.7 mA typ 3.8 mA max. at 3.0V DD 1.5 A typ max Freq: 4 MHz max 2.5V to 5.5V DD 2.7 mA typ. at 5.5V ...
Page 152
... Rext in kOhm. ) current VRL VRH LVD Advance Information T +85°C for industrial and A T +70°C for commercial A Conditions = 4 MHz 5.5V (Note MHz 5. 4.0V + 4.0V 4. 4.0V = 5.5V, A/D on, not converting Any of the BOR BG VRL VRH 1999 Microchip Technology Inc. ...
Page 153
... For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula The current is the additional current consumed when the peripheral is enabled. This current should be added to the base ( 1999 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C 0°C Sym Min Typ† Max Units 2.5 — ...
Page 154
... I C compliant For entire V range DD Note1 4.5V V 5.5V DD For entire V range compliant For entire V range DD Note1 = 5V PIN Pin at hi- PIN DD impedance Pin at hi- PIN DD impedance V V PIN XT, HS and LP PIN DD osc configuration I = 8.5 mA 4. 1.6 mA 4.5V - +85 C 1999 Microchip Technology Inc. ...
Page 155
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 1999 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) Operating temperature -40° ...
Page 156
... VREFSO I — — -5* VREFSI — 1 TBD OUT I — 1 TBD* OUT V / OUT 50* — — Advance Information Section 15.1 and Section 15.2. Units Conditions load on VRL load on VRH. ppm/°C Note Isource = mV/mA Isink = V/V 1999 Microchip Technology Inc. ...
Page 157
... Regulation DD D424* Low-voltage Detect Hysteresis * These parameters are characterized but not tested. Note 1: Production tested at Tamb = 25°C. Specifications over temp limits ensured by characterization. 1999 Microchip Technology Inc. V LHYS (LVDIF can be cleared in software anytime during the gray area) -40°C T +85°C for industrial and A 0° ...
Page 158
... TCV — 15 OUT V / — — BOR TBD — BHYS I — 10 BOR Advance Information (device not in Brown-out Reset time out Section 15.1 and Max Units Conditions 2.66 2.86 V 4.46 4.78 50 ppm/°C 50 V/V 100 1999 Microchip Technology Inc. ...
Page 159
... Uppercase letters and their meanings Fall H High I Invalid (Hi-impedance) L Low only AA output access BUF Bus free specifications only Hold ST DAT DATA input hold STA START condition 1999 Microchip Technology Inc. (Commercial, Industrial specifications only specifications only) T Time osc OSC1 SCK T0CKI t1 T1CKI ...
Page 160
... Load condition Pin 464 for all pins except OSC2, but including PORTD and PORTE outputs as L ports 15 pF for OSC2 output Note: PORTD and PORTE are not implemented on the PIC16C773. DS30275A-page 160 Load condition Pin Advance Information 1999 Microchip Technology Inc. ...
Page 161
... Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. 1999 Microchip Technology Inc ...
Page 162
... Max Units Conditions 75 200 ns Note 1 75 200 ns Note 1 35 100 ns Note 1 35 100 ns Note 1 — 0. Note 1 CY — — ns Note 1 — — ns Note 1 50 150 ns — — ns — — ns — — — — — — ns — — ns 1999 Microchip Technology Inc. ...
Page 163
... T Brown-out Reset pulse width BOR * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 1999 Microchip Technology Inc Min Typ† Max 100 — ...
Page 164
... Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30275A-page 164 T BGAP Min Typ† Max — 30 TBD Advance Information V = 1.2V BGAP Units Conditions s Defined as the time between the instant that the bandgap is enabled and the moment that the bandgap reference voltage is stable. 1999 Microchip Technology Inc. ...
Page 165
... Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power down current spec includes any such leakage from the A/D module current is from External V +, REF REF 3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 1999 Microchip Technology Inc. Min Typ† Max Units — — 12 bits bit — ...
Page 166
... C ). HOLD If the A/D clock source is selected as RC, a time added CY before the A/D clock starts. This allows the SLEEP instruction to be executed. 1999 Microchip Technology Inc. ...
Page 167
... These parameters are characterized but not tested. † Data in “Typ” column unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following T 2: See Section 11.6 for minimum conditions. 1999 Microchip Technology Inc. 131 130 ...
Page 168
... Must also meet parameter 47 — — ns — — ns — — ns — — ns — — prescale value ( — — prescale value ( — — ns — — ns — 50 kHz — 7Tosc — 1999 Microchip Technology Inc. ...
Page 169
... TccF CCP1 and CCP2 output fall time * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 1999 Microchip Technology Inc for load conditions. ...
Page 170
... These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30275A-page 170 65 62 Min Typ† Max Units PIC16LC774 35 — — 10 Advance Information 63 Conditions — — ns — ...
Page 171
... Data in “Typ” column unless otherwise stated. These parameters are for design guidance only and are not tested. 1999 Microchip Technology Inc. 121 Min PIC16C774/773 — PIC16LC774/773 — PIC16C774/773 — PIC16LC774/773 — PIC16C774/773 — PIC16LC774/773 — 125 126 Min Typ† (DT setup time) 15 — (DT hold time) 15 — Advance Information PIC16C77X 122 Typ† ...
Page 172
... PIC16C77X NOTES: DS30275A-page 172 Advance Information 1999 Microchip Technology Inc. ...
Page 173
... C. ’Max’ or ’min’ represents (mean + (mean - 3 ) respectively, where Graphs and Tables not available at this time. 1999 Microchip Technology Inc. is standard deviation, over the whole temperature range. Advance Information PIC16C77X ...
Page 174
... PIC16C77X NOTES: DS30275A-page 174 Advance Information 1999 Microchip Technology Inc. ...
Page 175
... Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 1999 Microchip Technology Inc. Example PIC16C773-20/SP ...
Page 176
... XXXXXXXXXXXX XXXXXXXXXXXX AABBCDE 44-Lead MQFP XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX AABBCDE 44-Lead PLCC XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX AABBCDE DS30275A-page 176 Example PIC16C774-04/P 9912SAA Example Example PIC16C774 -04/PT 9911HAT Example PIC16C774 -20/PQ 9904SAT Example PIC16C774 -04/L 9903SAT Advance Information PIC16C774/JW 9905HAT 1999 Microchip Technology Inc. ...
Page 177
... Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.” 1999 Microchip Technology Inc ...
Page 178
... Microchip Technology Inc. ...
Page 179
... Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.” 1999 Microchip Technology Inc ...
Page 180
... MILLIMETERS* NOM MAX 0.65 28 1.73 1.86 1.99 0.66 0.91 1.17 0.05 0.13 0.21 10.20 10.33 5.20 5.29 5.38 7.65 7.78 7.90 0.13 0.13 0.25 0.13 0.13 0.25 0.38 0.51 0. 0.00 0.13 0.25 0.13 0.18 0.22 0.25 0.32 0. 1999 Microchip Technology Inc. ...
Page 181
... Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.” 1999 Microchip Technology Inc ...
Page 182
... Microchip Technology Inc. ...
Page 183
... Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.” JEDEC equivalent:MS-026 ACB 1999 Microchip Technology Inc 45° ...
Page 184
... Microchip Technology Inc. ...
Page 185
... Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions “D” or “E.” JEDEC equivalent:MO-047 AC 1999 Microchip Technology Inc 35° ...
Page 186
... PIC16C77X NOTES: DS30275A-page 186 Advance Information 1999 Microchip Technology Inc. ...
Page 187
... SS SS • RB1 Added SS now ST vs. TTL • RB2 Added AN8 • RB3 Added AN9 and LVDIN 1999 Microchip Technology Inc. Revision Description PIC16C773 10 channels, 12 bits yes 40-pin PDIP, 40-pin windowed CERDIP, 44-pin TQFP, 44-pin MQFP, 44-pin PLCC Program Memory Differences ...
Page 188
... PIC16C77X NOTES: DS30275A-page 188 Advance Information 1999 Microchip Technology Inc. ...
Page 189
... Buffer Full Status bit, BF .................................................... 54 Bus Arbitration ................................................................... 90 Bus Collision Section ....................................................................... 90 Bus Collision During a RESTART Condition ...................... 93 Bus Collision During a Start Condition ............................... 91 Bus Collision During a Stop Condition ............................... 94 1999 Microchip Technology Inc. PIC16C77X C Capture (CCP Module) ...................................................... 48 Block Diagram ........................................................... 48 CCP Pin Configuration .............................................. 48 CCPR1H:CCPR1L Registers .................................... 48 Changing Between Capture Prescalers .................... 48 Software Interrupt ...
Page 190
... PSP Read/Write Enable (PSPIE Bit) ......................... 19 RB0/INT Enable (INTE Bit) ........................................ 18 SSP Enable (SSPIE Bit) ............................................ 19 TMR0 Overflow Enable (T0IE Bit) ............................. 18 TMR1 Overflow Enable (TMR1IE Bit) ........................ 19 TMR2 to PR2 Match Enable (TMR2IE Bit) ................ 19 USART Receive Enable (RCIE Bit) ........................... 19 USART Transmit Enable (TXIE Bit) ........................... 19 Preliminary 1999 Microchip Technology Inc. ...
Page 191
... Read/Write Enable (PSPIE Bit) .................................. 19 Read/Write Flag (PSPIF Bit) ...................................... 20 Select (PSPMODE Bit) .................................. 34, 35, 37 Write Waveforms ....................................................... 37 PCL Register ................................................................ 13, 14 PCLATH Register .................................................. 13, 14, 15 1999 Microchip Technology Inc. PIC16C77X PCON Register .......................................................... 23, 133 BOR Bit ...................................................................... 23 POR Bit ...................................................................... 23 PICDEM-1 Low-Cost PICmicro Demo Board .................. 146 PICDEM-2 Low-Cost PIC16CXX Demo Board ................ 146 PICDEM-3 Low-Cost PIC16CXXX Demo Board ...
Page 192
... Block Diagram ......................................................... 131 Reset Conditions for All Registers ........................... 134 Reset Conditions for PCON Register ...................... 133 Reset Conditions for Program Counter .................... 133 Reset Conditions for STATUS Register ................... 133 Restart Condition Enabled bit, RSE ................................... 56 Revision History ............................................................... 187 RSE ................................................................................... 56 Preliminary 1999 Microchip Technology Inc. ...
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... SSPSR ................................................................. 59, 64 SSPSTAT ............................................................. 54, 64 TMR2 Output for Clock Shift ................................ 45 SSP SSP I C Operation ..................................................... 63 1999 Microchip Technology Inc. PIC16C77X SSP Module SPI Master Mode ....................................................... 59 SPI Master./Slave Connection ................................... 58 SPI Slave Mode ......................................................... 60 SSPCON1 Register ................................................... 63 SSP Overflow Detect bit, SSPOV ...................................... 64 SSPADD Register .............................................................. 14 SSPBUF ...................................................................... 15, 64 SSPBUF Register ...
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... Transmission ................................................... 108 Synchronous Slave Mode ........................................ 110 Transmit Data, 9th Bit (TX9D) ................................... 97 Transmit Enable (TXEN Bit) ...................................... 97 Transmit Enable (TXIE Bit) ........................................ 19 Transmit Enable, Nine-bit (TX9 Bit) ........................... 97 Transmit Flag (TXIE Bit) ............................................ 20 Transmit Shift Register Status (TRMT Bit) ................ 97 TXSTA Register ......................................................... 97 Preliminary 1999 Microchip Technology Inc. ...
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... WDT Reset, Normal Operation ................ 131, 133, 134 WDT Reset, SLEEP ......................................... 133, 134 Waveform for General Call Address Sequence ................. 69 WCOL .................................................. 55, 74, 79, 82, 85, 87 WCOL Status Flag ............................................................. 74 Write Collision Detect bit, WCOL ....................................... 55 WWW, On-Line Support ...................................................... 4 1999 Microchip Technology Inc. PIC16C77X Preliminary DS30275A-page 195 ...
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... T1SYNC ............................................. T1CON<2> T2CKPS1:T2CKPS0 .......................... T2CON<1:0> TMR1CS ............................................ T1CON<1> TMR1IE .............................................. PIE1<0> TMR1IF .............................................. PIR1<0> TMR1ON ............................................ T1CON<0> TMR2IE .............................................. PIE1<1> TMR2IF .............................................. PIR1<1> TMR2ON ............................................ T2CON<2> TO ...................................................... STATUS<4> TOUTPS3:TOUTPS0 ......................... T2CON<6:3> TRMT ................................................. TXSTA<1> TX9 .................................................... TXSTA<6> TX9D .................................................. TXSTA<0> TXEN ................................................. TXSTA<5> TXIE ................................................... PIE1<4> TXIF ................................................... PIR1<4> UA ...................................................... SSPSTAT<1> WCOL ................................................ SSPCON<7> Z ......................................................... STATUS<2> Preliminary 1999 Microchip Technology Inc. ...
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... Trademarks: The Microchip name, logo, PIC, PICmicro, PICSTART, PICMASTER and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Flex ROM, MPLAB and fuzzy- LAB are trademarks and SQTP is a service mark of Micro- chip in the U ...
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... Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS30275A-page 198 Total Pages Sent FAX: (______) _________ - _________ N Literature Number: DS30275A 1998 Microchip Technology Inc. ...
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... The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 1999 Microchip Technology Inc. /XX XXX Examples: ...
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... Serialized Quick Turn Programming (SQTP service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system ...