PIC18F64J90-I/PT Microchip Technology, PIC18F64J90-I/PT Datasheet - Page 215
PIC18F64J90-I/PT
Manufacturer Part Number
PIC18F64J90-I/PT
Description
Microcontroller
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F63J11-IPT.pdf
(36 pages)
3.PIC18F63J90-IPT.pdf
(416 pages)
4.PIC18F63J90-IPT.pdf
(22 pages)
5.PIC18F63J90-IPT.pdf
(4 pages)
6.PIC18F63J90-IPT.pdf
(6 pages)
7.PIC18F63J90-IPT.pdf
(6 pages)
8.PIC18F63J90-IPT.pdf
(12 pages)
Specifications of PIC18F64J90-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
Number Of I /o
51
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F64J90-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F63J11-IPT PDF datasheet #2
- PIC18F63J90-IPT PDF datasheet #3
- PIC18F63J90-IPT PDF datasheet #4
- PIC18F63J90-IPT PDF datasheet #5
- PIC18F63J90-IPT PDF datasheet #6
- PIC18F63J90-IPT PDF datasheet #7
- PIC18F63J90-IPT PDF datasheet #8
- Current page: 215 of 416
- Download datasheet (4Mb)
17.4.4.5
When the CKP bit is cleared, the SCL output is forced
to ‘0’. However, clearing the CKP bit will not assert the
SCL output low until the SCL output is already sam-
pled low. Therefore, the CKP bit will not assert the
SCL line until an external I
FIGURE 17-14:
2010 Microchip Technology Inc.
WR
SSPCON
SDA
SCL
CKP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Clock Synchronization and
the CKP bit
CLOCK SYNCHRONIZATION TIMING
2
C master device has
DX
Master device
asserts clock
PIC18F85J90 FAMILY
already asserted the SCL line. The SCL output will
remain low until the CKP bit is set and all other
devices on the I
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCL (see
Figure 17-14).
Master device
deasserts clock
2
C bus have deasserted SCL. This
DS39770C-page 215
DX – 1
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