PIC18F8722T-I/PT Microchip Technology, PIC18F8722T-I/PT Datasheet - Page 2

• Manufacturer Part Number: PIC18F8722T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,80PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F8722T-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164136 - DEVELOPMENT KIT FOR PIC18XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6627/6722/8627/8722
4. Module: MSSP (I
5. Module: Enhanced Universal
DS80343B-page 2
If the module is in I
performs clock stretching, the first clock pulse after
the slave releases the SCL line may be narrower
than the configured clock width. This may result in
the slave missing the first clock in the next
transmission/reception.
Work around
If the module is in I
the slave perform clock stretching. Alternately, the
master can slow down the SCL clock frequency to
a level where the slave can detect the narrowed
clock pulse.
Date Codes that pertain to this issue:
All engineering and production devices.
In rare situations when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled (the SPEN
• The EUSART is re-enabled (RCSTAx <7> = 1)
• A two-cycle instruction is executed
Work around
Add a 2-T
1.
2.
3.
4.
5.
Date Codes that pertain to this issue:
All engineering and production devices.
(RCSTAx <7>) bit = 0)
Disable the receive interrupts:
• For RCSTA1 – RC1IE bit (PIE1<5>) = 0
• For RCSTA2 – RC2IE bit (PIE3<5>) = 0
Disable the EUSART:
• For RCSTA1 – SPEN bit (RCSTA1<7>) = 0
• For RCSTA2 – SPEN bit (RCSTA2<7>) = 0
Re-enable the EUSART (RCSTAx <7> = 1).
(See step 1.)
Re-enable the receive interrupts:
• For RCSTA1 – RC1IE bit (PIE1<5>) = 1
• For RCSTA2 – RC2IE bit (PIE3<5>) = 1
Execute a NOP instruction.
(This is the second T
(This is the first T
CY
Synchronous Asynchronous
(EUSART)
delay after re-enabling the EUSART.
2
2
C Master mode and the slave
2
C Master mode, do not have
C™ Master)
CY
CY
delay.)
delay.)
6. Module: Timer1
When Timer1 is running on the Timer1 oscillator, if
Sleep mode is executed immediately after loading
Timer 1 with 0xFFFF, the Timer1 interrupt will not
get set on the first overflow from 0xFFFF to
0x0000.
All subsequent overflows, from 0xFFFF to 0x0000,
will work correctly.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
© 2009 Microchip Technology Inc.