S29AL004D70TFI010 Spansion Inc., S29AL004D70TFI010 Datasheet - Page 15

• Manufacturer Part Number: S29AL004D70TFI010
• Description: Flash Memory IC
• Manufacturer: Spansion Inc.

Specifications of S29AL004D70TFI010

• Memory Size: 4Mbit
• Memory Configuration: 512K X 8 / 256K X 16
• Ic Interface Type: Parallel
• Access Time: 70ns
• Memory Case Style: TSOP
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

February 18, 2005 S29AL004D_00_A1
Sector
SA0
Automatic Sleep Mode
RESET#: Hardware Reset Pin
Output Disable Mode
A17
0
is in the standby mode, but the standby current is greater. The device requires
standard access time (t
standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.
In the iDC Characteristics table, I
specification.
The automatic sleep mode minimizes Flash device energy consumption. The de-
vice automatically enables this mode when addresses remain stable for t
ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control
signals. Standard address access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and always available to the
system. I
current specification.
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the RESET# pin is driven low for at least a period of t
device immediately terminates any operation in progress, tristates all output
pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The op-
eration that was interrupted should be reinitiated once the device is ready to
accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at V
at V
The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin re-
mains a 0 (busy) until the internal reset operation is complete, which requires a
time of t
BY# to determine whether the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing (RY/BY# pin is 1), the reset
operation is completed within a time of t
The system can read data t
Refer to the tables
to
When the OE# input is at V
are placed in the high impedance state.
Figure 14, on page 38
Table 2. S29AL004D Top Boot Block Sector Addresses (Sheet 1 of 2)
IL
SS
A16
±0.3 V, the device draws CMOS standby current (I
but not within V
0
READY
CC4
A d v a n c e
A15
in the iDC Characteristics table represents the automatic sleep mode
0
(during Embedded Algorithms). The system can thus monitor RY/
A14
AC Characteristics‚ on page 37
X
SS
CE
±0.3 V, the standby current is greater.
for the timing diagram.
) for read access when the device is in either of these
IH
A13
RH
I n f o r m a t i o n
X
, output from the device is disabled. The output pins
after the RESET# pin returns to V
A12
CC3
S29AL004D
X
and I
READY
Sector Size
(Kbytes/
Kwords)
CC4
64/32
(not during Embedded Algorithms).
represents the standby current
for RESET# parameters and
Address Range
00000h–0FFFFh
CC4
Address Range (in hexadecimal)
). If RESET# is held
(x8)
IH
.
ACC
RP
, the
+ 30
Address Range
00000h–07FFFh
(x16)
13