A1323LLHLT Allegro Microsystems Inc, A1323LLHLT Datasheet - Page 2
![IC SENSOR HALL EFFECT SOT23W](/photos/19/49/194943/620-sot-23w_sml.jpg)
A1323LLHLT
Manufacturer Part Number
A1323LLHLT
Description
IC SENSOR HALL EFFECT SOT23W
Manufacturer
Allegro Microsystems Inc
Type
Linear - Ratiometricr
Datasheet
1.A1321ELHLT-T.pdf
(13 pages)
Specifications of A1323LLHLT
Sensing Range
2.375mV/G ~ 2.625mV/G
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
8mA
Current - Output (max)
10mA
Output Type
Digital, Open Drain
Features
High Sensitivity
Operating Temperature
-40°C ~ 150°C
Package / Case
SOT-23W
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features and Benefits
▪ Temperature-stable quiescent output voltage
▪ Precise recoverability after temperature cycling
▪ Output voltage proportional to magnetic flux density
▪ Ratiometric rail-to-rail output
▪ Improved sensitivity
▪ 4.5 to 5.5 V operation
▪ Immunity to mechanical stress
▪ Solid-state reliability
▪ Robust EMC protection
Packages: 3 pin SOT23W (suffix LH), and
3 pin SIP (suffix UA)
Not to scale
A1321-DS, Rev. 23
V+
0.1 F
VCC
Ratiometric Linear Hall Effect Sensor ICs
Functional Block Diagram
for High-Temperature Operation
Amp
Gain
A1321, A1322, and A1323
Description
The A132X family of linear Hall-effect sensor ICs are optimized,
sensitive, and temperature-stable. These ratiometric Hall-effect
sensor ICs provide a voltage output that is proportional to the
applied magnetic field. The A132X family has a quiescent
output voltage that is 50% of the supply voltage and output
sensitivity options of 2.5 mV/G, 3.125 mV/G, and 5m V/G.
The features of this family of devices are ideal for use in the
harsh environments found in automotive and industrial linear
and rotary position sensing systems.
Each device has a BiCMOS monolithic circuit which integrates
a Hall element, improved temperature-compensating circuitry
to reduce the intrinsic sensitivity drift of the Hall element,
a small-signal high-gain amplifier, and a rail-to-rail low-
impedance output stage.
A proprietary dynamic offset cancellation technique, with
an internal high-frequency clock, reduces the residual offset
voltage normally caused by device overmolding, temperature
dependencies, and thermal stress. The high frequency clock
allows for a greater sampling rate, which results in higher
accuracy and faster signal processing capability. This technique
produces devices that have an extremely stable quiescent output
voltage, are immune to mechanical stress, and have precise
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GND
Control
Offset
Out
Trim
VOUT