A3250LLTTR Allegro Microsystems Inc, A3250LLTTR Datasheet - Page 12
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A3250LLTTR
Manufacturer Part Number
A3250LLTTR
Description
IC SW HALL EFFECT UNI SOT-89
Manufacturer
Allegro Microsystems Inc
Type
Unipolar Switchr
Datasheet
1.A3251EUA-T.pdf
(16 pages)
Specifications of A3250LLTTR
Sensing Range
50G
Voltage - Supply
4.2 V ~ 24 V
Current - Supply
10mA
Current - Output (max)
20mA
Output Type
Digital, Open Collector
Features
Regulated Voltage
Operating Temperature
-40°C ~ 150°C
Package / Case
SOT-89-3
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3250LLTTR
Manufacturer:
MAXIM
Quantity:
1 940
A3250
A3251
Enabling Addressing Mode.
keying sequence used to enable the bitfield addressing mode. As
shown in figure 4, this segment consists of one short V
seven or more V
supply interruptions. This sequence is designed to prevent the
device from being programmed accidentally, such as by noise on
the supply line.
Address Selection.
target bitfield address, is indicated by a series of VPM pulses,
as shown in figure 3. When provisionally trying a value, this
sequence is followed by a short V
delimit the address and set the corresponding bitfield. When
permanently setting a bitfield, the V
longer period of time, suffienct to not only set the bitfield to 1,
but also to blow the bitfield fuse.
Lock Bit Programming.
is programmed, and all of the corresponding bitfield-level fuses
are blown, the device-level fuse should be blown. To do so, the
lock bit (bitfield address 65) should be encoded as 1 and have
its fuse blown. This is done in the same manner as permanently
setting the other bitfields, as shown in figure 6.
and
PM
pulses, and one short V
After addressing mode is enabled, the
After the desired B
The first segment of code is a
PH
PH
pulse, which serves to
pulse is continued for a
PH
OP
pulse, with no
calibration value
Field-Programmable, Chopper-Stabilized,
PH
pulse,
Unipolar Hall-Effect Switches
V
V
V
V
V
V
V
V
V
PM
PM
PH
PH
PH
PM
PL
PL
PL
0
0
0
V+
V+
V+
Figure 6. Pulse sequence to encode lock bit
Figure 4. Addressing mode enable pulse sequence
Figure 5. Pulse sequence to select addresses
Falling edge of final B
7 pulses
Enable
Address 1
115 Northeast Cutoff, Box 15036
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Encode Lock Bit
Minimum 7 pulses
Address 2
OP
address digit
65 pulses
Address
Address n ( ≤ 63)
t
Blow
t
t
11