NTHS0603N10N1502JE Vishay, NTHS0603N10N1502JE Datasheet

THERMISTOR NTC 15K OHM 5% 0603

NTHS0603N10N1502JE

Manufacturer Part Number
NTHS0603N10N1502JE
Description
THERMISTOR NTC 15K OHM 5% 0603
Manufacturer
Vishay
Series
NTHSr

Specifications of NTHS0603N10N1502JE

Resistance In Ohms @ 25°c
15K
Resistance Tolerance
±5%
B Value Tolerance
±3%
B25/75
3500K
Mounting Type
Surface Mount
Package / Case
0603 (1608 Metric)
Lead Free Status / RoHS Status
Lead free by exemption / RoHS Compliant
B0/50
-
B25/50
-
B25/85
-
B25/100
-
Operating Temperature
-
Power - Max
-
Lead Length
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
541-1114-2

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
NTHS0603N10N1502JE
Manufacturer:
VISHAY/威世
Quantity:
20 000
S29GL-N MirrorBit
S29GL064N, S29GL032N
64 Megabit, 32 Megabit
3.0-Volt only Page Mode Flash Memory
Featuring 110 nm MirrorBit Process Technology
Data Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See
Publication Number S29GL-N_01
®
Notice On Data Sheet Designations
Flash Family
Revision 12
Issue Date October 29, 2008
for definitions.
S29GL-N MirrorBit
®
Flash Family Cover Sheet

Related parts for NTHS0603N10N1502JE

NTHS0603N10N1502JE Summary of contents

Page 1

S29GL-N MirrorBit S29GL064N, S29GL032N 64 Megabit, 32 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 110 nm MirrorBit Process Technology Data Sheet Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product ...

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Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all ...

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S29GL-N MirrorBit S29GL064N, S29GL032N 64 Megabit, 32 Megabit 3.0 Volt-only Page Mode Flash Memory Featuring 110 nm MirrorBit Process Technology Data Sheet Distinctive Characteristics Architectural Advantages Single power supply operation Manufactured on 110 nm MirrorBit process technology Secured Silicon Sector ...

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General Description The S29GL-N family of devices are 3.0-Volt single-power Flash memory manufactured using 110 nm MirrorBit technology. The S29GL064N is a 64-Mb device organized as 4,194,304 words or 8,388,608 bytes. The S29GL032N is a 32-Mb device organized as 2,097,152 ...

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Table of Contents Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Figures Figure 3.1 48-Pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Tables Table 6.1 S29GL032N Ordering Options Table 8.1 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Product Selector Guide Part Number Speed Option Max. Access Time (ns) Max. CE# Access Time (ns) Max. Page Access Time (ns) Max. OE# Access Time (ns) 2. Block Diagram RY/BY RESET# WE# State Control WP#/ACC ...

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Connection Diagrams Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (TSOP and BGA). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for ...

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October 29, 2008 S29GL-N_01_12 Figure 3.3 64-ball Fortified BGA S29GL064N, S29GL032N (Models 01, 02, 03, 04, V1, V2 only) Top View, Balls Facing Down NC on S29GL032N ...

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A6 A13 WE# A3 RY/BY Figure 3.4 48-ball Fine-pitch BGA (VBK 048) S29GL064N, S29GL032N (Models 03, 04 only) Top View, Balls Facing Down ...

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Pin Descriptions Pin A21–A0 A20–A0 DQ7–DQ0 DQ14–DQ0 DQ15/A-1 CE# OE# WE# WP#/ACC ACC WP# RESET# RY/BY# BYTE October 29, 2008 S29GL-N_01_12 Description 22 ...

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Logic Symbols Figure 5.1 S29GL064N Logic Symbol (Models 01, 02, V1, V2) 22 A21–A0 DQ15–DQ0 CE# OE# WE# WP#/ACC RESET# V RY/BY# IO BYTE# Figure 5.3 S29GL064N Logic Symbol (Models 06, 07, V6, V7) 22 A21–A0 DQ15–DQ0 CE# OE# ...

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Ordering Information–S29GL032N S29GL032N Standard Products Standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: S29GL032N PACKING TYPE 0 2 ...

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Ordering Information–S29GL064N S29GL064N Standard Products Standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: S29GL064N PACKING TYPE 0 = ...

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Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch ...

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Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. The page size ...

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Standby Mode When the system is not reading or writing to the device, it can be placed in to standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, ...

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Table 8.2 S29GL032N (Models 01, 02, V1, V2) Sector Addresses Sector Size 8-bit (KB/ Address Sector A20-A15 Kwords) Range SA0 000000 64/32 000000h–00FFFFh SA1 000001 64/32 010000h–01FFFFh SA2 000010 64/32 020000h–02FFFFh SA3 000011 64/32 030000h–03FFFFh SA4 000100 64/32 040000h–04FFFFh SA5 ...

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Table 8.3 S29GL032N (Model 03) Top Boot Sector Addresses Sector Size 8-bit (KB/ Address Sector A20–A12 Kwords) Range SA0 000000xxx 64/32 000000h–00FFFFh SA1 000001xxx 64/32 010000h–01FFFFh SA2 000010xxx 64/32 020000h–02FFFFh SA3 000011xxx 64/32 030000h–03FFFFh SA4 000100xxx 64/32 040000h–04FFFFh SA5 000101xxx ...

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Table 8.4 S29GL032N (Model 04) Bottom Boot Sector Addresses Sector Size 8-bit (KB/ Address Sector A20–A12 Kwords) Range SA0 000000000 8/4 000000h–001FFFh SA1 000000001 8/4 002000h–003FFFh SA2 000000010 8/4 004000h–005FFFh SA3 000000011 8/4 006000h–007FFFh SA4 000000100 8/4 008000h–009FFFh SA5 000000101 ...

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Table 8.5 S29GL064N (Models 01, 02, V1, V2) Sector Addresses (Sheet Sector Size 8-bit (KB/ Address Sector A21–A15 Kwords) Range SA0 0000000 64/32 000000h–00FFFFh SA1 0000001 64/32 010000h–01FFFFh SA2 0000010 64/32 020000h–02FFFFh SA3 0000011 64/32 030000h–03FFFFh SA4 ...

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Table 8.5 S29GL064N (Models 01, 02, V1, V2) Sector Addresses (Sheet Sector Size 8-bit (KB/ Address Sector A21–A15 Kwords) Range SA46 0101110 64/32 2E0000h–2EFFFFh SA47 0101111 64/32 2F0000h–2FFFFFh SA48 0110000 64/32 300000h–30FFFFh SA49 0110001 64/32 310000h–31FFFFh SA50 ...

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Table 8.6 S29GL064N (Model 03) Top Boot Sector Addresses (Sheet Sector Size 8-bit (KB/ Address Sector A21–A12 Kwords) Range SA23 0010111xxx 64/32 170000h–17FFFFh SA24 0011000xxx 64/32 180000h–18FFFFh SA25 0011001xxx 64/32 190000h–19FFFFh SA26 0011010xxx 64/32 1A0000h–1AFFFFh SA27 0011011xxx ...

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Table 8.7 S29GL064N (Model 04) Bottom Boot Sector Addresses (Sheet Sector Size 8-bit (KB/ Address Sector A21–A12 Kwords) Range SA0 0000000000 8/4 000000h–001FFFh SA1 0000000001 8/4 002000h–003FFFh SA2 0000000010 8/4 004000h–005FFFh SA3 0000000011 8/4 006000h–007FFFh SA4 0000000100 ...

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Table 8.7 S29GL064N (Model 04) Bottom Boot Sector Addresses (Sheet Sector Size 8-bit (KB/ Address Sector A21–A12 Kwords) Range SA91 1010100xxx 64/32 540000h–54FFFFh SA92 1010101xxx 64/32 550000h–55FFFFh SA93 1010110xxx 64/32 560000h–56FFFFh SA94 1010111xxx 64/32 570000h–57FFFFh SA95 1011000xxx ...

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Table 8.8 S29GL064N (Models 06, 07, V6, V7) Sector Addresses (Sheet Sector A21–A15 SA19 0010011 SA20 0010100 SA21 0010101 SA22 0010110 SA23 0010111 SA24 0011000 SA25 0011001 SA26 0011010 SA27 0011011 SA28 0011100 SA29 0011101 SA30 0011110 ...

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Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding ...

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Advanced Sector Protection The device features several levels of sector protection, which can disable both the program and erase operations in certain sectors: 8.9.1 Persistent Sector Protection A command sector protection method that replaces the old 12 V controlled ...

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Lock Register The Lock Register consists of 3 bits (DQ2, DQ1, and DQ0). These DQ2, DQ1, DQ0 bits of the Lock Register are programmable by the user. Users are not allowed to program both DQ2 and DQ1 bits of ...

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Volatile. Individual PPB bits are set with a program command but must all be cleared as a group through an erase command. The PPB Lock Bit adds an additional level of protection. Once all PPB bits are programmed to the ...

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Persistent Protection Bit Lock (PPB Lock Bit) A global volatile bit. When set to the “freeze state”, the PPB bits cannot be changed. When cleared to the “unfreeze state”, the PPB bits are changeable. There is only one PPB ...

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Password Sector Protection The Password Sector Protection method allows an even higher level of security than the Persistent Sector Protection method. There are two main differences between the Persistent Sector Protection and the Password Sector Protection methods: When the ...

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Persistent Protection Bit Lock (PPB Lock Bit) A global volatile bit. The PPB Lock Bit is a volatile bit that reflects the state of the Password Protection Mode Lock Bit after power-up reset. If the Password Protection Mode Lock ...

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Customer Lockable: Secured Silicon Sector NOT Programmed or Protected At the Factory Unless otherwise specified, the device is shipped such that the customer may program and protect the 256- byte Secured Silicon sector. The system may program the Secured ...

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Write Pulse Glitch Protection Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. 8.17.3 Logical Inhibit Write cycles are inhibited by holding any one of OE CE# ...

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Addresses (x16) Addresses (x8) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Note CFI data related to V and time-outs may differ from actual V CC tables to obtain the V range for particular part numbers. ...

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Addresses (x16) Addresses (x8) 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch October 29, 2008 S29GL-N_01_12 Table ...

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Addresses (x16) Addresses (x8) 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h Table 9.4 Primary Vendor-Specific Extended Query Data Description 80h ...

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Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. Table 10.1 on page 51 Writing incorrect address and data values or writing them in the improper sequence may place the device ...

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Autoselect Command Sequence The autoselect command sequence allows the host system to read several identifier codes at specific addresses: Device ID, Cycle 1 Device ID, Cycle 2 Device ID, Cycle 3 Secured Silicon Sector Factory Protect Sector Protect Verify ...

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Any bit in a word cannot be programmed from 0 back Attempting may cause the device to set DQ5=1, or cause DQ7 and DQ6 status bits to indicate the operation was successful. However, a ...

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Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data loading stage of the operation. Write data other than the Confirm Command after the specified number of data load ...

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Notes 1. When Sector Address is specified, any address in the selected sector is acceptable. However, when loading Write-Buffer address locations with data, all addresses must fall within the selected Write-Buffer Page. 2. DQ7 may change simultaneously with DQ5. Therefore, ...

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Note See Table 10.1 on page 51 10.5 Program Suspend/Program Resume Command Sequence The Program Suspend command allows the system to interrupt a programming operation or a Write to Buffer programming operation so that data can be read from any ...

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Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the ...

Page 48

Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed ...

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Notes 1. See Table 10.1 and Table 10.3 2. See the section on DQ3 for information on the sector erase timer. October 29, 2008 S29GL-N_01_12 Figure 10.4 Erase Operation START Write ...

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Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during ...

Page 51

Command Definitions Table 10.1 Command Definitions (x16 Mode, BYTE Command Sequence (Note 1) Read (Note 5) 1 Reset (Note 6) 1 Manufacturer ID 4 Device ID (Note 8) 6 Device ID 4 Secured Silicon Sector Factory Protect ...

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Command Sequence (Notes) Addr Command Set Entry 3 555 (Note 5) Program (Note Read (Note Command Set Exit 2 XX (Note 7) Command Set Entry 3 555 (Note 5) Program (Note ...

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Table 10.3 Command Definitions (x8 Mode, BYTE Command Sequence (Note 1) Read (Note 6) 1 Reset (Note 7) 1 Manufacturer ID 4 Device ID (Note 9) 6 Device ID 4 Secured Silicon Sector Factory Protect 4 Sector Protect ...

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Command Sequence (Notes) Addr Command Set Entry 3 AAA (Note 5) Program (Note 6) 2 XXX Read (Note Command Set Exit 2 XXX (Note 7) Command Set Entry 3 AAA (Note 5) Program (Note 8) 2 ...

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Write Operation Status The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 10.5 on page 60 and DQ6 each offer a method for determining whether a ...

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Notes Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be ...

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DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device entered the Erase Suspend mode. Toggle Bit I may be read at any ...

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Note The system should recheck the toggle bit even if DQ5 = 1 because the toggle bit may stop toggling as DQ5 changes to 1. See the subsections on DQ6 and DQ2 for more information. 10.14 DQ2: Toggle Bit II ...

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Figure 10.6 on page 58 toggle bit timing diagram. form. 10.15 Reading Toggle Bits DQ6/DQ2 Refer to Figure 10.6 on page 58 toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle ...

Page 60

DQ1: Write-to-Buffer Abort DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a 1. The system must issue the Write-to-Buffer-Abort-Reset command sequence to return the device to reading array data. See Write Buffer on page ...

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Absolute Maximum Ratings Storage Temperature, Plastic Packages Ambient Temperature with Power Applied Voltage with Respect to Ground Output Short Circuit Current Notes 1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or I/Os ...

Page 62

DC Characteristics Table 13.1 DC Characteristics, CMOS Compatible Parameter Symbol Parameter Description (Notes) I Input Load Current (Note Input Load Current LIT I Output Leakage Current Initial Read Current (Note 1) CC1 ...

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Test Conditions Note Diodes are IN3064 or equivalent. Output Load Output Load Capacitance, C (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 14.1 Key to Switching ...

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AC Characteristics Parameter JEDEC Std Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV CE t Page Access Time PACC t t Output ...

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Addresses CE# OE# WE# Outputs RESET# RY/BY A23-A2 A1-A0* Data Bus CE# OE# Note * Figure shows device in word mode. Addresses are A1–A-1 for byte mode. October 29, 2008 S29GL-N_01_12 ...

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Parameter JEDEC Std. t RESET# Pin Low (During Embedded Algorithms) to Read Mode Ready RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode t Ready (See Note) t RESET# Pulse Width RP t Reset High Time Before Read RH ...

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Parameter JEDEC Std Write Cycle Time AVAV Address Setup Time AVWL AS t Address Setup Time to OE# low during toggle bit polling ASO t t Address Hold Time WLAX AH t Address Hold Time ...

Page 68

Program Command Sequence (last two cycles Addresses 555h CE# OE# WE Data RY/BY VCS Notes program address program data Illustration shows device in word mode. V ...

Page 69

Figure 15.7 Chip/Sector Erase Operation Timings Erase Command Sequence (last two cycles Addresses 2AAh CE Data RY/BY# t VCS V CC Notes sector address (for Sector Erase), VA ...

Page 70

Figure 15.9 Toggle Bit Timings (During Embedded Algorithms) Addresses CE# t OEH WE# OE Valid Data DQ6 / DQ2 RY/BY# Note VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, ...

Page 71

Table 15.4 Alternate CE# Controlled Erase and Program Operations Parameter JEDEC Std Write Cycle Time AVAV Address Setup Time AVWL Address Hold Time ELAX Data Setup Time DVEH DS ...

Page 72

Figure 15.11 Alternate CE# Controlled Write (Erase/Program) Operation Timings Addresses WE# OE# CE# Data t RESET# RY/BY# Notes 1. Figure indicates last two bus cycles of a program or erase operation program address sector address, ...

Page 73

Erase And Programming Performance Parameter Sector Erase Time Chip Erase Time Total Write Buffer Program Time (Notes 3, 5) Total Accelerated Effective Write Buffer Program Time (Notes 4, 5) Chip Program Time Notes 1. Typical program and erase times ...

Page 74

Physical Dimensions 17.1 TS048—48-Pin Standard Thin Small Outline Package (TSOP) STANDARD PIN OUT (TOP VIEW SEE DETAIL B SEE DETAIL B - SEE DETAIL A SEE DETAIL A R 0˚ PARALLEL ...

Page 75

TS056—56-Pin Standard Thin Small Outline Package (TSOP) STANDARD PIN OUT (TOP VIEW SEE DETAIL 0. (N/2 TIPS) B SEE DETAIL A θ° PARALLEL TO SEATING PLANE DETAIL ...

Page 76

VBK048—Ball Fine-pitch Ball Grid Array (BGA) 8.15x 6.15 mm Package D INDEX MARK PIN A1 CORNER 10 TOP VIEW A SEATING PLANE A1 SIDE VIEW PACKAGE VBK 048 JEDEC N/A 8. 6.15 mm NOM PACKAGE SYMBOL MIN ...

Page 77

LAA064—64-Ball Fortified Ball Grid Array (BGA Package PACKAGE LAA 064 JEDEC N/A 13. 11.00 mm PACKAGE SYMBOL MIN NOM MAX A --- --- 1.40 A1 0.40 --- --- A2 0.60 --- --- D ...

Page 78

LAE064-64-Ball Fortified Ball Grid Array (BGA Package PACKAGE JEDEC 9. 9.00 mm SYMBOL MIN A --- A1 0. φb 0. ...

Page 79

Revision History Section Revision 01 (February 12, 2007) Initial release. Revision 02 (February 26, 2007) Global Replaced LAE064 package with LAA064. Page Mode Read Corrected bit ranges in first paragraph. Erase And Programming Performance Modified maximum sector erase time ...

Page 80

Section Revision 11 (August 5, 2008) DC Characteristics Changed Note 1 in Table DC Characteristics- CMOS Compatible Ordering Information Added LAE064 package option Connection Diagram Figure 3.3; Title changed to 64ball Fortified BGA Physical Dimensions Added LAE064 package option Revision ...

Page 81

Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated ...

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