CDB4228A Cirrus Logic Inc, CDB4228A Datasheet - Page 5

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CDB4228A

Manufacturer Part Number
CDB4228A
Description
Development Kit
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CDB4228A

Silicon Manufacturer
Cirrus Logic
Application Sub Type
Codec
Kit Application Type
Audio / Video / TV
Silicon Core Number
CS4228A
Features
PC Software Provides Easy To Use Board & Device Control
Kit Contents
Evaluation Board
Rohs Compliant
No
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
PLD can support division ratios of 1, 2, 3, and 4 to
support MCLK frequencies of 128, 256, 384, and
512 Fs respectively. The proper division ratio can
be selected in the GUI in PP mode, or S5 in EX-
TRNL mode.
4.3
The digital audio port (DAP) provides an interface
to the CODEC serial audio clocks and data. The
DAP can be used to interface to external com-
pressed audio decoder systems such as the CS492x
or CS49300 families of digital signal processors for
ease in evaluating complete audio system solu-
tions. MCLK, LRCLK, and SCLK are bidirectional
signals. The direction of these signals can be con-
trolled by the GUI in PP mode, or S5 switches in
EXTRNL mode. The direction of SCLK and LR-
CLK is always selected as a pair.
4.4
Master clock (MCLK) for the evaluation board can
come from one of three sources: the on-board
CS8414 receiver, the on-board oscillator, or an ex-
ternal source via the DAP port. One of the three
sources is selected by multiplexer U2 which is con-
trolled via the GUI in PP mode or the S5 switches
in EXTRNL mode. The on-board oscillator provid-
ed with the board is 12.288 MHz for evaluation at
256 Fs at a 48kHz sample rate, or 128 Fs at a 96kHz
sample rate. The oscillator is socketed for easy re-
placement and can be powered down with header
JP1 to prevent asynchronous clock interference
when the S/PDIF receiver is being used.
The MCLK multiplexer adds a small amount of
clock jitter to the MCLK signal, which has a very
slight effect on converter performance. The system
can be evaluated without the buffer by installing a
3x2 pin header in JP2, and removing R3. A 2-sock-
et shorting jumper is then installed in JP2 to select
the system MCLK source. Refer to Figure 15.
DS511DB1
Digital Audio Port
Master Clock
4.5
The serial data format for the evaluation board is
set by the GUI in PP mode or by S5 switches in EX-
TRNL mode. Not all serial modes of each device
are supported. SMODE 4 and 5 are not supported
by the transmitter. Two serial formats are common
to all three devices; I2S, 16 to 24 bits/sample, and
right justified, 16 bits/sample.
Each of the three SDIN inputs to the CS4228A
comes from a multiplexer within the PLD and can be
individually sourced from the CS8414 receiver or
from the DAP. The multiplexer can be disabled and
jumpers JP3-JP5 can be used to select the source.
5. ANALOG INPUT
Analog inputs to the CDB4228A are single ended,
with a full scale of 2V RMS (5.66V p-p). The inputs
are AC coupled, then converted to a differential sig-
nal with a 2.3V common mode voltage derived from
the 5V supply. The differential signal is then anti-
aliased with a passive filter, Fc = 200 kHz, before
being sent to the ADC as shown in Figure 2.
6. ANALOG OUTPUT
The analog outputs from the DACs are buffered with
a 2-pole active butterworth filter, Fc = 50 kHz. The
filter has a DC gain of 1.56V/V for a 2V RMS full
scale output. For a lower cost alternative, the outputs
can be filtered with a single pole passive filter with
Fc = 50 kHz and RL > 10k ohms as shown in Figure
11. The outputs also have a mute circuit that is con-
trolled by the MUTEC pin on the CS4228A.
7. EXTERNAL CONTROL MODE
The CDB4228A system can be controlled without
using a PC by connecting a host controller to the
EXTRNL CTRL port. All board functions set by
the parallel port are available to the user on the 10
position DIP switch, S5. There are three parameters
on S5; board level serial mode, MCLK multiplex-
ing, and S/PDIF transmitter clock divider control.
On S5, an open switch denotes a one for that bit po-
sition.
Serial Data Format
CDB4228A
5

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