EVAL-ADUC842QSZ Analog Devices Inc, EVAL-ADUC842QSZ Datasheet - Page 22

• Manufacturer Part Number: EVAL-ADUC842QSZ
• Description: Analog MCU Evaluation Board
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC842QSZ

• Silicon Manufacturer: Analog Devices
• Core Architecture: 8052
• Silicon Core Number: ADuC842
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: ADUC8xx
• Contents: Evaluation Board, Power Supply, Cable, Software and Documentation
• Development Tool Type: Hardware - Eval/Demo Board
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC824
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADuC841/ADuC842/ADuC843
SPECIAL FUNCTION REGISTER BANKS
All registers except the program counter and the four general-
purpose register banks reside in the special function register
(SFR) area. The SFR registers include control, configuration,
and data registers, which provide an interface between the CPU
and other on-chip peripherals. Figure 27 shows a full SFR
memory map and SFR contents on reset. Unoccupied SFR
locations are shown dark-shaded in the figure (NOT USED).
Unoccupied locations in the SFR address space are not
SFR MAP KEY:
1
2
3
NOTES
I2CSI/MDO
FFH
F7H
EFH
E7H
DFH
D7H
CFH
C7H
BFH
B7H
AFH
A7H
9FH
97H
8FH
87H
SFRs WHOSE ADDRESS ENDS IN 0H OR 8H ARE BIT ADDRESSABLE.
THE PRIMARY FUNCTION OF PORT1 IS AS AN ANALOG INPUT PORT; THEREFORE, TO ENABLE THE DIGITAL SECONDARY FUNCTIONS ON THESE
PORT PINS, WRITE A 0 TO THE CORRESPONDING PORT 1 SFR BIT.
CALIBRATION COEFFICIENTS ARE PRECONFIGURED ON POWER-UP TO FACTORY CALIBRATED VALUES.
ADCI
PRE3
SM0
ISPI
TF2
TF1
PSI
CY
RD
EA
0
0 F6H
0 EEH
0 E6H
0
0
0
0
0
1
0
1
0
1 96H
0
1 86H
I2CGC/MDE
FEH
DEH
D6H
CEH
C6H
BEH
B6H
AEH
A6H
9EH
8EH
WCOL
PADC
EADC
EXF2
PRE2
DMA
SM1
TR1
WR
AC
1
0
0 F5H
0
0 E5H
0
0
0
0
0
1
0
0
1 95H
0
1 85H
I2C1O1MCO
FDH
EDH
CCONV
DDH
D5H
CDH
C5H
BDH
B5H
ADH
A5H
9DH
8DH
RCLK
PRE1
SPE
SM2
PT2
ET2
TF0
F0
T1
0
0 F4H
0 ECH
0 E4H
0
0
0
0 C4H
0
1
0
1 A4H
0
1 94H
0
1 84H
I2C1O0/MDI
FCH
SCONV
DCH
D4H
CCH
BCH
B4H
ACH
9CH
8CH
TCLK
PRE0
SPIM
REN
RS1
TR0
PS
ES
T0
0
0 F3H
0 EBH
0 E3H
0
0
0
1
0
1
0
1 A3H
0
1 93H
0
1 83H
FBH
DBH
D3H
CBH
C3H
BBH
B3H
ABH
9BH
8BH
EXEN2
CPOL
WDIR
I2CM
INT1
CS3
RS0
TB8
PT1
ET1
IE1
DEFAULT VALUE
SFR ADDRESS
0
0 F2H
0 EAH
0 E2H
0
0
0
0
0
1
0
1 A2H
0
1 92H
0
1 82H
MNEMONIC
FAH
DAH
D2H
CAH
C2H
BAH
B2H
AAH
9AH
8AH
CPHA
I2CRS I2CTX
WDS
INT0
RB8
CS2
TR2
PX1
EX1
OV
IT1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
F9H
F1H
E9H
E1H
D9H
D1H
C9H
C1H
B9H
B1H
A9H
A1H
99H
91H
89H
81H
SPR1
CNT2
T2EX
WDE
CS1
PT0
TxD
ET0
Figure 27. Special Function Register Locations and Reset Values
IE0
FI
TI
THESE BITS ARE CONTAINED IN THIS BYTE.
0
0 F0H
0 E8H
0 E0H
0
0
0
0
0
1
0
1 A0H
0
1
0
1 80H
F8H
D8H
D0H
C8H
C0H
B8H
B0H
A8H
98H
90H
88H
WDWR
CAP2
SPR0
I2CI
CS0
PX0
RxD
EX0
IT0
T2
89H
RI
P
IE0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
88H
IT0
Rev. 0 | Page 22 of 88
0
E0H
ADCCON2
D8H
C8H
C0H
B0H
D0H
B8H
A8H
A0H
98H
F8H
F0H
E8H
90H
88H
80H
SPICON
I2CCON
WDCON
T2CON
SCON
TCON
PSW
ACC
P1
P3
P2
P0
IP
IE
B
1, 2
88H
1
1
1
FFH
FFH
FFH
1
00H
1
00H
00H
1
00H
00H
00H
FFH
04H
00H
00H
00H
00H
10H
TCON
1
1
1
1
1
1
1
1
1
00H
ADCOFSL
ADCDATAL
B1H
RESERVED
TIMECON HTHSEC
A1H
F9H
F1H
RESERVED
RESERVED
D9H
RESERVED
B9H
A9H
99H
89H
81H
RESERVED
91H
I2CADD1
PWM0L
implemented, i.e., no register exists at this location. If an
unoccupied location is read, an unspecified value is returned.
SFR locations reserved for on-chip testing are shown lighter
shaded (RESERVED) and should not be accessed by user
software. Sixteen of the SFR locations are also bit addressable
and denoted by 1 in Figure 27, i.e., the bit addressable SFRs are
those whose address ends in 0H or 8H.
DAC0L
ECON
TMOD
SBUF
IEIP2
SP
A0H
7FH
00H
00H
00H
00H
00H
00H
07H
00H
00H
3
MNEMONIC
DEFAULT VALUE
SFR ADDRESS
ADCOFSH
B2H
ADCDATAH
RESERVED RESERVED RESERVED RESERVED
A2H
FAH
F2H
RESERVED
RESERVED
DAH
D2H
CAH
RESERVED RESERVED
9AH
8AH
82H
C2H
92H
I2CADD2
RCAP2L
PWM0H
I2CDAT
DAC0H
CHIPID
DMAL
DPL
TL0
7FH
00H
20H
00H
00H
00H
XXH
00H
00H
00H
00H
00H
3
ADCGAINL
B3H
9BH
FBH
F3H
RESERVED
RESERVED
RESERVED
D3H
CBH
A3H
8BH
83H
RESERVED RESERVED
93H
RCAP2H
I2CADD3
I2CADD
PWM1L
DAC1L
DMAH
SEC
DPH
TL1
7FH
00H
00H
00H
00H
00H
00H
00H
55H
00H
3
ADCGAINH
B4H
FCH
F4H
RESERVED
RESERVED
RESERVED
D4H
CCH
BCH
8CH
84H
A4H
NOT USED
NOT USED
EDATA1
PWM1H
DAC1H
DMAP
MIN
DPP
TL2
TH0
00H
00H
00H
00H
00H
00H
00H
00H
00H
3
ADCCON3
9DH
FDH
F5H
RESERVED
RESERVED
RESERVED
RESERVED
CDH
RESERVED
BDH
8DH
DACCON
NOT USED
A5H
NOT USED
RESERVED
EDATA2
HOUR
T3FD
TH2
TH1
04H
00H
00H
00H
00H
00H
00H
9EH
AEH
PWMCON
RESERVED RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
C6H
BEH
A6H
NOT USED
NOT USED
RESERVED
EDATA3
T3CON
EDARL
INTVAL
00H
00H
00H
00H
00H
D7H
AFH
ADCCON1
B7H
A7H
C7H
RESERVED
F7H
EFH
RESERVED
DFH DEH
RESERVED
BFH
87H
PSMCON
PLLCON
NOT USED
NOT USED
EDATA4
CFG841/
CFG842
SPIDAT
EDARH
DPCON
PCON
SPH
00H
40H
00H
00H
53H
00H
00H
00H
00H