EVAL-ADUC842QSZ Analog Devices Inc, EVAL-ADUC842QSZ Datasheet - Page 44

• Manufacturer Part Number: EVAL-ADUC842QSZ
• Description: Analog MCU Evaluation Board
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC842QSZ

• Silicon Manufacturer: Analog Devices
• Core Architecture: 8052
• Silicon Core Number: ADuC842
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: ADUC8xx
• Contents: Evaluation Board, Power Supply, Cable, Software and Documentation
• Development Tool Type: Hardware - Eval/Demo Board
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC824
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADuC841/ADuC842/ADuC843
Mode 4: Dual NRZ 16-Bit ∑-∆ DAC
Mode 4 provides a high speed PWM output similar to that of a
∑
equal to 16.777216 MHz. In this mode, P2.6 and P2.7 are
updated every PWM clock (60 ns in the case of 16 MHz). Over
any 65536 cycles (16-bit PWM) PWM0 (P2.6) is high for
PWM0H/L cycles and low for (65536 – PWM0H/L) cycles.
Similarly, PWM1 (P2.7) is high for PWM1H/L cycles and low
for (65536 – PWM1H/L) cycles.
For example, if PWM1H is set to 4010H (slightly above one
quarter of FS), then typically P2.7 will be low for three clocks
and high for one clock (each clock is approximately 60 ns). Over
every 65536 clocks, the PWM compensates for the fact that the
output should be slightly above one quarter of full scale by
having a high cycle followed by only two low cycles.
For faster DAC outputs (at lower resolution), write 0s to the
LSBs that are not required. If, for example, only 12-bit perform-
ance is required, write 0s to the four LSBs. This means that a 12-bit
accurate
writing 0s to the 8 LSBs gives an 8-bit accurate
at 65 kHz.
Mode 5: Dual 8-Bit PWM
In Mode 5, the duty cycle of the PWM outputs and the resolu-
tion of the PWM outputs are individually programmable. The
maximum resolution of the PWM output is 8 bits. The output
resolution is set by the PWM1L and PWM1H SFRs for the P2.6
and P2.7 outputs, respectively. PWM0L and PWM0H sets the
duty cycles of the PWM outputs at P2.6 and P2.7, respectively.
Both PWMs have the same clock source and clock divider.
16.777MHz
-∆ DAC. Typically, this mode is used with the PWM clock
PWM0H/L = C000H
PWM1H/L = 4000H
16-BIT
16-BIT
16-BIT
16-BIT
∑
-∆ DAC output can occur at 4.096 kHz. Similarly
LATCH
Figure 51. PWM Mode 4
CARRY OUT AT P1.0
CARRY OUT AT P2.7
16-BIT
16-BIT
60 µ s
60 µ s
0
0
1
0
∑
1
0
-∆ DAC output
1
1
0
0
1
0
1
0
Rev. 0 | Page 44 of 88
Mode 6: Dual RZ 16-Bit ∑-∆ DAC
Mode 6 provides a high speed PWM output similar to that of a
∑
the key difference is that Mode 6 provides return-to-zero (RZ)
∑
DAC outputs. The RZ mode ensures that any difference in the
rise and fall times will not affect the
the RZ mode halves the dynamic range of the
from 0 V–AV
should be used with a PWM clock divider of 4.
If PWM1H is set to 4010H (slightly above one quarter of FS),
typically P2.7 will be low for three full clocks (3 × 60 ns), high
for half a clock (30 ns), and then low again for half a clock
(30 ns) before repeating itself. Over every 65536 clocks, the
PWM will compensate for the fact that the output should be
slightly above one quarter of full scale by leaving the output
high for two half clocks in four. The rate at which this happens
depends on the value and degree of compensation required.
-∆ DAC. Mode 6 operates very similarly to Mode 4. However,
-∆ DAC output. Mode 4 provides non-return-to-zero
PWM1H/L = 4000H
PWM0H/L = C000H
4MHz
16-BIT
16-BIT
0, 3/4, 1/2, 1/4, 0
16-BIT
16-BIT
DD
down to 0 V–AV
LATCH
PWM COUNTERS
Figure 52. PWM Mode 5
Figure 53. PWM Mode 6
CARRY OUT AT P2.6
CARRY OUT AT P2.7
16-BIT
16-BIT
DD
/2. For best results, this mode
∑
-∆ DAC INL. However,
240 µ s
240 µ s
0 1
0
0
∑
1
-∆ DAC outputs
0 1
1
P2.6
PWM1H
PWM0H
0
P2.7
PWM1L
PWM0L
0
0
∑
1
-∆
0
1
0