EVAL-ADUC842QSZ Analog Devices Inc, EVAL-ADUC842QSZ Datasheet - Page 58

• Manufacturer Part Number: EVAL-ADUC842QSZ
• Description: Analog MCU Evaluation Board
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC842QSZ

• Silicon Manufacturer: Analog Devices
• Core Architecture: 8052
• Silicon Core Number: ADuC842
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: ADUC8xx
• Contents: Evaluation Board, Power Supply, Cable, Software and Documentation
• Development Tool Type: Hardware - Eval/Demo Board
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC824
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADuC841/ADuC842/ADuC843
In general-purpose I/O port mode, Port 2 pins that have 1s
written to them are pulled high by the internal pull-ups
(Figure 60) and, in that state, can be used as inputs. As inputs,
Port 2 pins being pulled externally low source current because
of the internal pull-up resistors. Port 2 pins with 0s written to
them drive a logic low output voltage (V
sinking 1.6 mA.
P2.6 and P2.7 can also be used as PWM outputs. When they are
selected as the PWM outputs via the CFG841/CFG842 SFR, the
PWM outputs overwrite anything written to P2.6 or P2.7.
Port 3
Port 3 is a bidirectional port with internal pull-ups directly
controlled via the P3 SFR. Port 3 pins that have 1s written to
them are pulled high by the internal pull-ups and, in that state,
can be used as inputs. As inputs, Port 3 pins being pulled
externally low source current because of the internal pull-ups.
Port 3 pins with 0s written to them will drive a logic low output
voltage (V
have various secondary functions as described in Table 26. The
alternate functions of Port 3 pins can be activated only if the
corresponding bit latch in the P3 SFR contains a 1. Otherwise,
the port pin is stuck at 0.
Table 26. Port 3 Alternate Pin Functions
Pin No.
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
TO LATCH
INTERNAL
LATCH
LATCH
FROM
PORT
WRITE
READ
READ
BUS
PIN
Q
OL
Alternate Function
RxD (UART Input Pin) (or Serial Data I/O in Mode 0)
TxD (UART Output Pin) (or Serial Clock Output in Mode 0)
INT0 (External Interrupt 0)
INT1 (External Interrupt 1)/PWM 1/MISO
T0 (Timer/Counter 0 External Input)
PWM External Clock/PWM 0
T1 (Timer/Counter 1 External Input)
WR (External Data Memory Write Strobe)
RD (External Data Memory Read Strobe)
) and are capable of sinking 4 mA. Port 3 pins also
DELAY
2 CLK
Figure 60. Internal Pull-Up Configuration
Figure 59. Port 2 Bit Latch and I/O Buffer
LATCH
CL
D
Q
Q
ADDR
* SEE FOLLOWING FIGURE FOR
DETAILS OF INTERNAL PULL-UP
CONTROL
Q4
Q1
DV
DD
Q2
OL
DV
) and are capable of
DD
DV
DD
Q3
DV
DV
DD
DD
INTERNAL
PULL-UP*
P2.x
PIN
Px.x
PIN
Rev. 0 | Page 58 of 88
P3.3 and P3.4 can also be used as PWM outputs. When they are
selected as the PWM outputs via the CFG841/CFG842 SFR, the
PWM outputs overwrite anything written to P3.4 or P3.3.
Additional Digital I/O
In addition to the port pins, the dedicated SPI/I
and SDATA/MOSI) also feature both input and output func-
tions. Their equivalent I/O architectures are illustrated in
Figure 62 and Figure 64, respectively, for SPI operation and in
Figure 63 and Figure 65 for I
mode (SPE = 0), the strong pull-up FET (Q1) is disabled,
leaving only a weak pull-up (Q2) present. By contrast, in SPI
mode (SPE = 1) the strong pull-up FET (Q1) is controlled
directly by SPI hardware, giving the pin push-pull capability.
In I
operate in parallel to provide an extra 60% or 70% of current
sinking capability. In SPI mode (SPE = 1), however, only one of
the pull-down FETs (Q3) operates on each pin, resulting in sink
capabilities identical to that of Port 0 and Port 2 pins. On the
input path of SCLOCK, notice that a Schmitt trigger conditions
the signal going to the SPI hardware to prevent false triggers
(double triggers) on slow incoming edges. For incoming signals
from the SCLOCK and SDATA pins going to I
filter conditions the signals to reject glitches of up to 50 ns in
duration.
Notice also that direct access to the SCLOCK and SDATA/
MOSI pins is afforded through the SFR interface in I
mode. Therefore, if you are not using the SPI or I
you can use these two pins to give additional high current
digital outputs.
INTERNAL
TO LATCH
LATCH
(MASTER/SLAVE)
WRITE
2
HARDWARE SPI
READ
READ
C mode (SPE = 0), two pull-down FETs (Q3 and Q4)
BUS
PIN
Figure 62. SCLOCK Pin I/O Functional Equivalent in SPI Mode
SPE = 1 (SPI ENABLE)
Figure 61. Port 3 Bit Latch and I/O Buffer
LATCH
CL
D
Q
Q
ALTERNATE
ALTERNATE
SCHMITT
TRIGGER
FUNCTION
FUNCTION
OUTPUT
INPUT
2
C operation. Notice that in I
Q1
Q3
DV
DV
DD
DD
INTERNAL
PULL-UP*
* SEE PREVIOUS FIGURE
FOR DETAILS OF
INTERNAL PULL-UP
Q2 (OFF)
Q4 (OFF)
2
2
C pins (SCLOCK
C hardware, a
P3.x
PIN
2
C functions,
SCLOCK
2
C master
PIN
2
C