EVAL-ADUC842QSZ Analog Devices Inc, EVAL-ADUC842QSZ Datasheet - Page 66

• Manufacturer Part Number: EVAL-ADUC842QSZ
• Description: Analog MCU Evaluation Board
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC842QSZ

• Silicon Manufacturer: Analog Devices
• Core Architecture: 8052
• Silicon Core Number: ADuC842
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: ADUC8xx
• Contents: Evaluation Board, Power Supply, Cable, Software and Documentation
• Development Tool Type: Hardware - Eval/Demo Board
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC824
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADuC841/ADuC842/ADuC843
Mode 0: 8-Bit Shift Register Mode
Mode 0 is selected by clearing both the SM0 and SM1 bits in the
SFR SCON. Serial data enters and exits through RxD. TxD out-
puts the shift clock. Eight data bits are transmitted or received.
Transmission is initiated by any instruction that writes to SBUF.
The data is shifted out of the RxD line. The 8 bits are transmitted
with the least significant bit (LSB) first.
Reception is initiated when the receive enable bit (REN) is 1
and the receive interrupt bit (RI) is 0. When RI is cleared, the
data is clocked into the RxD line, and the clock pulses are
output from the TxD line.
Mode 1: 8-Bit UART, Variable Baud Rate
Mode 1 is selected by clearing SM0 and setting SM1. Each data
byte (LSB first) is preceded by a start bit (0) and followed by a
stop bit (1). Therefore, 10 bits are transmitted on TxD or are
received on RxD. The baud rate is set by the Timer 1 or Timer 2
overflow rate, or a combination of the two (one for transmission
and the other for reception).
Transmission is initiated by writing to SBUF. The write to SBUF
signal also loads a 1 (stop bit) into the 9th bit position of the
transmit shift register. The data is output bit by bit until the stop
bit appears on TxD and the transmit interrupt flag (TI) is
automatically set, as shown in Figure 72.
Reception is initiated when a 1-to-0 transition is detected on
RxD. Assuming a valid start bit is detected, character reception
continues. The start bit is skipped and the 8 data bits are
clocked into the serial port shift register. When all 8 bits have
been clocked in, the following events occur:
•
•
•
(SCON.1)
TxD
The 8 bits in the receive shift register are latched into SBUF.
The 9th bit (stop bit) is clocked into RB8 in SCON.
The receiver interrupt flag (RI) is set.
TI
START
BIT
Figure 72. UART Serial Port Transmission, Mode 1
D0
D1
D2
D3
D4
D5
I.E., READY FOR MORE DATA
D6
SET INTERRUPT
D7
STOP BIT
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This is the case if, and only if, all of the following conditions are
met at the time the final shift pulse is generated:
•
•
•
If any of these conditions is not met, the received frame is
irretrievably lost, and RI is not set.
Mode 2: 9-Bit UART with Fixed Baud Rate
Mode 2 is selected by setting SM0 and clearing SM1. In this
mode, the UART operates in 9-bit mode with a fixed baud rate.
The baud rate is fixed at Core_Clk/32 by default, although by
setting the SMOD bit in PCON, the frequency can be doubled
to Core_Clk/16. Eleven bits are transmitted or received: a start
bit (0), 8 data bits, a programmable 9th bit, and a stop bit (1).
The 9th bit is most often used as a parity bit, although it can be
used for anything, including a 9th data bit if required.
To transmit, the 8 data bits must be written into SBUF. The 9th
bit must be written to TB8 in SCON. When transmission is
initiated, the 8 data bits (from SBUF) are loaded onto the
transmit shift register (LSB first). The contents of TB8 are loaded
into the 9th bit position of the transmit shift register. The
transmission starts at the next valid baud rate clock. The TI flag
is set as soon as the stop bit appears on TxD.
Reception for Mode 2 is similar to that of Mode 1. The 8 data
bytes are input at RxD (LSB first) and loaded onto the receive
shift register. When all 8 bits have been clocked in, the following
events occur:
•
•
•
This is the case if, and only if, all of the following conditions are
met at the time the final shift pulse is generated:
•
•
•
If any of these conditions is not met, the received frame is
irretrievably lost, and RI is not set.
RI = 0
Either SM2 = 0 or SM2 = 1
The received stop bit = 1
The 8 bits in the receive shift register are latched into SBUF.
The 9th data bit is latched into RB8 in SCON.
The receiver interrupt flag (RI) is set.
RI = 0
Either SM2 = 0 or SM2 = 1
The received stop bit = 1