EVAL-ADUC842QSZ Analog Devices Inc, EVAL-ADUC842QSZ Datasheet - Page 74

• Manufacturer Part Number: EVAL-ADUC842QSZ
• Description: Analog MCU Evaluation Board
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC842QSZ

• Silicon Manufacturer: Analog Devices
• Core Architecture: 8052
• Silicon Core Number: ADuC842
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: ADUC8xx
• Contents: Evaluation Board, Power Supply, Cable, Software and Documentation
• Development Tool Type: Hardware - Eval/Demo Board
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC824
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADuC841/ADuC842/ADuC843
Power Consumption
The currents consumed by the various sections of the part are
shown in Table 40. The core values given represent the current
drawn by DV
pulled by the AV
not in use. The other on-chip peripherals (such as the watchdog
timer and the power supply monitor) consume negligible
current, and are therefore lumped in with the core operating
current here. Of course, the user must add any currents sourced
by the parallel and serial I/O pins, and sourced by the DAC, in
order to determine the total current needed at the supply pins.
Also, current drawn from the DV
mately 10 mA during Flash/EE erase and program cycles.
Table 40. Typical I
Core (Normal Mode)
ADC
DAC (Each)
Voltage Ref
Since operating DV
speed, the expressions for core supply current in Table 40 are
given as functions of M
value for M
the core at that oscillator frequency. Since the ADC and DACs
can be enabled or disabled in software, add only the currents
from the peripherals you expect to use. And again, do not forget
to include current sourced by I/O pins, serial port pins, DAC
outputs, and so forth, plus the additional current drawn during
Flash/EE erase and program cycles. A software switch allows the
chip to be switched from normal mode into idle mode, and also
into full power-down mode. Brief descriptions of idle and
power-down modes follow.
Power Saving Modes
In idle mode, the oscillator continues to run, but the core clock
generated from the PLL is halted. The on-chip peripherals
continue to receive the clock, and remain functional. The CPU
status is preserved with the stack pointer and program counter,
and all other internal registers maintain their data during idle
mode. Port pins and DAC output pins retain their states in this
mode. The chip recovers from idle mode upon receiving any
enabled interrupt, or upon receiving a hardware reset.
In full power-down mode, both the PLL and the clock to the
core are stopped. The on-chip oscillator can be halted or can
continue to oscillate, depending on the state of the oscillator
power-down bit in the PLLCON SFR. The TIC, being driven
directly from the oscillator, can also be enabled during power-
down. All other on-chip peripherals are, however, shut down.
Port pins retain their logic levels in this mode, but the DAC
output goes to a high impedance state (three-state). During full
CLK
DD
in hertz to determine the current consumed by
, while the rest (ADC, DAC, voltage ref) are
DD
DD
pin and can be disabled in software when
DD
V
(2.2 nA
1.7 mA
250 µA
200 µA
DD
of Core and Peripherals
current is primarily a function of clock
CLK
= 5 V
×
, the core clock frequency. Plug in a
M
CLK
)
DD
supply increases by approxi-
V
(1.4 nA
1.7 mA
200 µA
150 µA
DD
= 3 V
×
M
CLK
)
Rev. 0 | Page 74 of 88
power-down mode, the part consumes a total of approximately
20 µA. There are five ways of terminating power-down mode:
Asserting the RESET Pin (Pin 15)
Returns to normal mode. All registers are set to their default
state and program execution starts at the reset vector once the
RESET pin is de-asserted.
Cycling Power
All registers are set to their default state and program execution
starts at the reset vector approximately 128 ms later.
Time Interval Counter (TIC) Interrupt
Power-down mode is terminated, and the CPU services the TIC
interrupt. The RETI at the end of the TIC ISR returns the core
to the instruction after the one that enabled power-down.
I
Power-down mode is terminated, and the CPU services the
I
core to the instruction after the one that enabled power-down.
Note that the I
in the PCON SFR must be set to allow this mode of operation.
INT0 Interrupt
Power-down mode is terminated, and the CPU services the
INT0 interrupt. The RETI at the end of the ISR returns the core
to the instruction after the one that enabled power-down. The
INT0 pin must not be driven low during or within two machine
cycles of the instruction that initiates power-down mode. Note
that the INT0 power-down interrupt enable bit (INT0PD) in
the PCON SFR must be set to allow this mode of operation.
Power-On Reset (POR)
An internal POR is implemented on the ADuC841/ADuC842/
ADuC843.
3 V Part
For DV
As DV
approximately 128 ms before the part is released from reset. The
user must ensure that the power supply has reached a stable
2.7 V minimum level by this time. Likewise on power-down, the
internal POR holds the part in reset until the power supply has
dropped below 1 V. Figure 82 illustrates the operation of the
internal POR in detail.
DV
CORE RESET
2
2
C/SPI interrupt. The RETI at the end of the ISR returns the
C or SPI Interrupt
INTERNAL
DD
2.45V TYP
DD
1.0V TYP
DD
rises above 2.45 V, an internal timer times out for
below 2.45 V, the internal POR holds the part in reset.
2
C/SPI power-down interrupt enable bit (SERIPD)
Figure 82. Internal POR Operation
128ms TYP
128ms TYP
1.0V TYP