EVAL-ADUC842QSZ Analog Devices Inc, EVAL-ADUC842QSZ Datasheet - Page 78

• Manufacturer Part Number: EVAL-ADUC842QSZ
• Description: Analog MCU Evaluation Board
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC842QSZ

• Silicon Manufacturer: Analog Devices
• Core Architecture: 8052
• Silicon Core Number: ADuC842
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: ADUC8xx
• Contents: Evaluation Board, Power Supply, Cable, Software and Documentation
• Development Tool Type: Hardware - Eval/Demo Board
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC824
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADuC841/ADuC842/ADuC843
TIMING SPECIFICATIONS
Table 41. AV
unless otherwise noted
Parameter
ADuC842/ADuC843 CLOCK INPUT (External Clock Driven XTAL1)
t
t
t
t
t
1/t
t
t
1
2
3
4
5
6
CK
CKL
CKH
CKR
CKF
CORE
CYC
loaded V
AC inputs during testing are driven at DV
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the
C
ADuC842/ADuC843 internal PLL locks onto a multiple (512 times) of the 32.768 kHz external crystal frequency to provide a stable 16.78 MHz internal clock for the
This number is measured at the default Core_Clk operating frequency of 2.09 MHz.
ADuC842/ADuC843 machine cycle time is nominally defined as 1/Core_CLK.
shown in Figure 87.
system. The core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR.
LOAD
CORE
for all outputs = 80 pF, unless otherwise noted.
Parameter
ADuC841 CLOCK INPUT (External Clock Driven XTAL1)
t
t
t
t
t
1/t
t
t
CK
CKL
CKH
CKR
CKF
CORE
CYC
OH
CORE
/V
OL
level occurs, as shown in Figure 87.
DD
=2.7 V to 3.6 V or 4.75 V to 5.25 V, DV
DV
DD
– 0.5V
0.45V
XTAL1 Period
XTAL1 Width Low
XTAL1 Width High
XTAL1 Rise Time
XTAL1 Fall Time
ADuC842/ADuC843 Core Clock Frequency
ADuC842/ADuC843 Core Clock Period
ADuC842/ADuC843 Machine Cycle Time
XTAL1 Period
XTAL1 Width Low
XTAL1 Width High
XTAL1 Rise Time
XTAL1 Fall Time
ADuC841 Core Clock Frequency
ADuC841 Core Clock Period
ADuC841 Machine Cycle Time
DD
– 0.5 V for a Logic 1 and 0.45 V for Logic 0. Timing measurements are made at V
0.2DV
0.2DV
1, 2, 3
TEST POINTS
DD
DD
– 0.1V
+ 0.9V
t
CKH
Figure 87. Timing Waveform Characteristics
DD
Figure 86. XTAL1 Input
= 2.7 V to 3.6 V or 4.75 V to 5.25 V; all specifications T
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5
V
6
t
LOAD
CKL
4
Min
62.5
20
20
0.131
0.05
V
V
LOAD
LOAD
– 0.1V
+ 0.1V
t
CKR
t
CK
Variable External Crystal
Min
0.131
0.059
REFERENCE
POINTS
TIMING
32.768 kHz External Crystal
Typ
0.476
0.476
t
CKF
Typ
30.52
6.26
6.26
9
9
0.476
0.476
IH
min for Logic 1 and V
V
V
LOAD
LOAD
– 0.1V
– 0.1V
Max
1000
20
20
20
7.63
V
Max
16.78
7.63
LOAD
MIN
to T
IL
max for Logic 0, as
Unit
ns
ns
ns
ns
ns
MHz
µs
µs
MAX
,
Unit
µs
µs
µs
ns
ns
MHz
µs
µs