IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 99
IPR-XAUIPCS
Manufacturer Part Number
IPR-XAUIPCS
Description
IP CORE Renewal Of IP-XAUIPCS
Manufacturer
Altera
Datasheet
1.IP-XAUIPCS.pdf
(120 pages)
Specifications of IPR-XAUIPCS
Software Application
IP CORE, Interface And Protocols, ETHERNET
Supported Families
Stratix IV GT, Stratix V
Features
10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
Core Architecture
FPGA
Core Sub-architecture
Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
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Chapter 8: Low Latency PHY IP Core
Interfaces
Table 8–4. PMA Analog Options (Part 2 of 2)
Interfaces
Figure 8–2. Top-Level PMA Signals
Note to
(1) <n> is the number of channels or the number of PLLs. <d> is the deserialization factor.
December 2010 Altera Corporation
RX termination resistance
Receiver DC gain
Receiver static equalizer setting: 0–15
Avalon-ST Tx and Rx
Figure
to and from MAC
8–2:
Name
Avalon-MM PHY
Management
Interface
Figure 8–2
Stratix IV
Only
illustrates the top-level signals of the Low Latency PHY IP core.
OCT_85_OHMS
OCT_100_OHMS
OCT_120_OHMS
OCT_150_OHMS
0–4
tx_parallel_data<n>[<d>-1:0]
tx_parallel_clk[<n>-1:0]
rx_parallel_data<n>[<d>-1:0]
tx_ready[<n>-1:0]
rx_ready[<n>-1:0]
phy_mgmt_clk
phy_mgmt_reset
phy_mgmt_address[8:0]
phy_mgmt_writedata[31:0]
phy_mgmt_readdata[31:0]
phy_mgmt_write
phy_mgmt_read
phy_mgmt_waitrequest
pll_ref_clk
Value
Low Latency PHY IP Core Top-Level Signals
Indicates the value of the termination resistor for the receiver.
Sets the equalization DC gain using one of the following settings:
■
■
■
■
■
This option sets the equalizer control settings. The equalizer uses a
pass band filter. Specifying a low value passes low frequencies.
Specifying a high value passes high frequencies.
0–0 dB
1–3 dB
2–6 dB
3–9 dB
4–12 dB
rx_is_lockedtodata<n>[<n>-1:0]
rx_is_lockedtoref[<n>-1:0]
rx_coreclkin[<n>-1>:0]
tx_coreclkin[<n>-1:0]
pll_locked[<n>-1:0]
rx_serial_data<n>
rx_clkout[<n>-1:0]
tx_serial_data<n>
Description
Altera Transceiver PHY IP Core User Guide
tx_bitslip
Optional
Status
Serial
Data
8–5
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