IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 6

IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design

IP-10GETHERNET

Manufacturer Part Number
IP-10GETHERNET
Description
IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
Manufacturer
Altera
Datasheet

Specifications of IP-10GETHERNET

Software Application
IP CORE, Interface And Protocols, ETHERNET
Supported Families
Quartus II
Core Architecture
FPGA
Core Sub-architecture
Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
1–4
Table 1–4. New Features and Device Support History (Part 2 of 2)
10-Gbps Ethernet IP Datasheet
9.0 March 2009
8.1 November 2008
Notes to
(1) Preliminary support means the IP core meets all functional requirements, but may still be undergoing timing analysis for
(2) Full support means the IP core meets all functional and timing requirements for the device family and can be used in
the device family; it can be used in production designs with caution.
production designs.
Release
Table
1–4:
Initial release.
Added 2 input signals, xon_request and
xoff_request that request XON and XOFF pause
frames.
Support for 1 primary and 4 supplemental addresses.
64-bit counters shadow upper 32 bits.
Soft XAUI and MAC-only options.
New Features
Arria II GX
Arria GX
Stratix II
Stratix II GX
Stratix III
Stratix IV
Device Support
Added
© July 2010 Altera Corporation
Preliminary
Full
Full
Full
Full
Preliminary
Device Support
Revision History
(2)
Level

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