IP-SDRAM/HPDDR Altera, IP-SDRAM/HPDDR Datasheet

Page 1

... DDR and DDR2 SDRAM High-Performance 101 Innovation Drive San Jose, CA 95134 www.altera.com Controller User Guide Software Version: Document Date: March 2009 9.0 ...

Page 2

... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation ...

Page 3

... Simulate the System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4 MegaWizard Plug-In Manager Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4 Specify Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5 Simulate the Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8 Simulating Using NativeLink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8 IP Functional Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9 Compile the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13 Program Device and Implement the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14 Chapter 3. Parameter Settings Memory Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1 PHY Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3– ...

Page 4

... ECC Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10 Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11 Example Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12 Interfaces and Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14 Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14 Full Rate Write, Avalon-MM Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14 Full Rate Write, Native Interface Mode—Non-Consecutive Write . . . . . . . . . . . . . . . . . . . . . . . . 4–17 Half Rate Write, Avalon-MM Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20 Half Rate Write, Native Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22 Full Rate Read, Avalon-MM Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4– ...

Page 5

... HardCopy III HardCopy IV E © March 2009 Altera Corporation 1. About These MegaCore Functions functions. ® Item IP-SDRAM/HPDDR (DDR SDRAM) IP-SDRAM/HPDDR2 (DDR2 SDRAM) 00CO (ALTMEMPHY Megafunction) Device Family Full Preliminary Full Full Preliminary Preliminary DDR and DDR2 SDRAM High-Performance Controller User Guide Description 9 ...

Page 6

... Support for OpenCore Plus evaluation ■ ■ Support for the Quartus II IP Advisor ■ IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators General Description The Altera DDR and DDR2 SDRAM High-Performance Controller MegaCore functions provide simplified interfaces to industry-standard DDR SDRAM and DDR2 SDRAM ...

Page 7

... PLL and DLL. You can optionally instantiate the DLL outside the ALTMEMPHY megafunction to share the DLL between multiple instances of the ALTMEMPHY megafunction. The example design is a fully-functional design that you can simulate, synthesize, and use in hardware. The example driver is a self-test module that issues read and write commands to the controller and checks the read data to produce the pass/fail and test complete signals ...

Page 8

... Memory Dedicated Logic Registers M512 M4K 1,562 4 2 1,738 4 4 2,783 5 15 2,958 4 17 1,332 6 0 1,421 3 3 1,939 3 9 2,026 4 9 © March 2009 Altera Corporation ...

Page 9

... AFI mode (including ALTMEMPHY) for Stratix II and Stratix II GX devices. Table 1–6. Resource Utilization in Stratix II and Stratix II GX Devices Local Data Controller Rate Width (Bits) Half 32 64 256 288 Full 32 64 256 288 © March 2009 Altera Corporation Memory Width Combinational (Bits) ALUTs 8 2,683 16 2,905 64 4,224 72 4,478 8 2,386 16 ...

Page 10

... Chapter 1: About These MegaCore Functions Performance and Resource Utilization Dedicated Logic Memory Registers (M9K) 1,432 2 1,581 3 2,465 9 2,613 10 1,351 2 1,431 2 1,897 5 1,975 6 Dedicated Logic Memory Registers (M9K) 1,452 1 1,597 2 2,457 8 2,601 9 1,369 1 1,448 1 1,906 4 1,983 5 © March 2009 Altera Corporation ...

Page 11

... Chapter 1: About These MegaCore Functions Installation and Licensing Installation and Licensing The DDR and DDR2 SDRAM High-Performance Controller MegaCore functions are part of the MegaCore IP Library, which is distributed with the Quartus II software and downloadable from the Altera website, www.altera.com. f For system requirements and installation instructions, refer to Licensing for Windows and Linux Figure 1– ...

Page 12

... Your design stops working after the hardware evaluation time expires and the local_ready output goes low. DDR and DDR2 SDRAM High-Performance Controller User Guide Chapter 1: About These MegaCore Functions Installation and Licensing AN320: OpenCore Plus Evaluation © March 2009 Altera Corporation ...

Page 13

... DDR and DDR2 SDRAM High-Performance Controller MegaCore function and the Quartus II software. The sections in this chapter describe each stage. Figure 2–1. Design Flow © March 2009 Altera Corporation Select Design Flow MegaWizard Plug-In Manager Flow ...

Page 14

... Specify the required parameters on all pages in the Parameter Settings tab. DDR and DDR2 SDRAM High-Performance Controller User Guide SOPC Builder Flow Design directly from the DDR or DDR2 ■ SDRAM interface to peripheral device or devices Achieves higher-frequency operation ■ Chapter 2: Getting Started Select Flow ...

Page 15

... SDRAM memory contents from flash every time you reset. To calculate the Avalon-MM address equivalent of the memory address range 0×0 to 0×1f, multiply the memory address by the width of the memory interface data bus in bytes. For example, if your external memory data width is 8 bits in non-AFI mode, then the Reset Vector Offset should be 0× ...

Page 16

... SDRAM High-Performance Controller MegaCore function, and manually integrate the function into your design. 1 You can alternatively use the IP Advisor to help you start your DDR and DDR2 SDRAM High-Performance Controller MegaCore design. On the Quartus II Tools menu, point to Advisors, and then click IP Advisor. The IP Advisor guides you ...

Page 17

... If you generate the MegaCore function instance in a Quartus II project, you are prompted to add the .qip files to the current Quartus II project. When prompted to add the .qip files to your project, click Yes. The addition of the .qip files enables their visibility to Nativelink. Nativelink requires the .qip files to include libraries for simulation ...

Page 18

... If you launch IP Toolbench outside of the Pin Planner application, you must explicitly load this file to use Pin Planner. VHDL or Verilog HDL IP functional simulation model. Example self-checking test generator that matches your variation. Example top-level design file that you should set as your Quartus II project top level ...

Page 19

... Specification file that generates the <variation_name>_alt_mem_phy_dq_dqs file using the clearbox flow. Arria II GX devices only. Quartus II IP file for the PLL that your ALTMEMPHY variation uses that contains the files associated with this megafunction. The PLL megafunction file for your ALTMEMPHY variation, generated based on the language you chose in the MegaWizard Plug-In Manager ...

Page 20

... For more information on NativeLink, refer to the Simulation Tools Simulating Using NativeLink To set up simulation in the Quartus II software using NativeLink, follow these steps: 1. Create a custom variation with an IP functional simulation model, refer to step the “Specify Parameters” 2. Set the top-level entity to the example project. ...

Page 21

... For a complete MegaWizard Plug-In Manager system design example containing the DDR and DDR2 SDRAM high-performance controller MegaCore function, refer to Chapter 5, Example Design IP Functional Simulations For VHDL simulations with IP functional simulation models, perform the following steps: 1. Create a directory in the <project directory>\testbench directory. © March 2009 Altera Corporation ...

Page 22

... Compile the files into the appropriate library (AFI mode) as shown in The files are in VHDL93 format. Table 2–4. Files to Compile—VHDL IP Functional Simulation Models (Part Library File Name altera_mf <QUARTUS ROOTDIR>/eda/sim_lib/altera_mf_components.vhd <QUARTUS ROOTDIR>/eda/sim_lib/altera_mf.vhd lpm /eda/sim_lib/220pack ...

Page 23

... Chapter 2: Getting Started MegaWizard Plug-In Manager Flow Table 2–4. Files to Compile—VHDL IP Functional Simulation Models (Part Library File Name auk_ddr_hp_user_lib <QUARTUS ROOTDIR>/ libraries/vhdl/altera/altera_europa_support_lib.vhd <project directory>/<variation name>_phy_alt_mem_phy_seq_wrapper.vho <project directory>/<variation name>_auk_ddr_hp_controller_wrapper.vho <project directory>/<variation name>_phy.vho <project directory>/<variation name>.vhd <project directory>/<variation name>_example_top.vhd < ...

Page 24

... Table 2–5. Files to Compile—Verilog HDL IP Functional Simulation Models Library File Name altera_mf_ver <QUARTUS ROOTDIR>/eda/sim_lib/altera_mf.v lpm_ver /eda/sim_lib/220model.v sgate_ver eda/sim_lib/sgate.v <device name>_ver eda/sim_lib/<device name>_atoms.v eda/sim_lib/<device name>_hssi_atoms.v altera_ver eda/sim_lib/altera_primitives.v ALTGXB_ver (1) <device name>_mf.v <device name>_hssi_ver (1) <device name>_hssi_atoms.v auk_ddr_hp_user_lib <QUARTUS ROOTDIR>/ libraries/vhdl/altera/altera_europa_support_lib ...

Page 25

... If your design contains pin names that do not match the design, edit the <variation name>_pin_assignments.tcl file before you run the script. Follow these steps: a. Open <variation name>_pin_assignments.tcl file. b. Based on the flow you are using, set the sopc_mode value to Yes or No. ...

Page 26

... DDR and DDR2 SDRAM High-Performance Controller User Guide Program Device and Implement the Design II logic analyzer to your design, refer to ® Driver. 2–8) or program your targeted Altera Chapter 2: Getting Started AN 380: Test DDR or © March 2009 Altera Corporation ...

Page 27

... Specifies the controller/PHY interface. Refer to the PHY Interface Megafunction User Guide (ALTMEMPHY) information. This option is only in SOPC Builder Flow. Turn on if you want to improve your system efficiency when your system has multiple controllers. Refer to the External Memory PHY Interface Megafunction User Guide (ALTMEMPHY) for more information ...

Page 28

... DDR and DDR2 SDRAM High-Performance Controller User Guide Chapter 3: Parameter Settings Controller Settings © March 2009 Altera Corporation ...

Page 29

... The controller does not do any access reordering. f For more information on the ALTMEMPHY megafunction, refer to the Memory PHY Interface Megafunction User Guide © March 2009 Altera Corporation 4. Functional Description External (ALTMEMPHY). DDR and DDR2 SDRAM High-Performance Controller User Guide ...

Page 30

... ALTMEMPHY Megafunction Timer Logic Initialization State Machine Main State Machine Bank Write Data Management Tracking Logic Logic Chapter 4: Functional Description Block Description mem_a mem_ba mem_cas_n mem_cke mem_cs_n mem_dq mem_dqs mem_dm mem_odt ( 1 ) mem_ras_n mem_we_n Address and Command Decode ALTMEMPHY ...

Page 31

... Chapter 4: Functional Description Block Description The blocks in Command FIFO This FIFO allows the controller to buffer up to four consecutive read or write commands built from logic elements, and stores the address, read or write flag, and burst count information. If this FIFO fills up, the local_ready signal to the user is deasserted until the main state machine takes a command from the FIFO ...

Page 32

... DQ pins at the correct time. ODT Generation Logic The ODT generation logic (not shown) calculates when and for how long to enable the ODT outputs. It also decides which ODT bit to enable, based on the number of chip selects in the system. 1 DIMM ( Chip Selects) ■ ...

Page 33

... Bus commands control SDRAM devices using combinations of the mem_ras_n, mem_cas_n, and mem_we_n signals. For example clock cycle where all three signals are high, the associated command operation (NOP). A NOP command is also indicated when the chip select signal is not asserted. standard SDRAM bus commands. Table 4–1. Bus Commands ...

Page 34

... Write 167 4 Read Write 333 5 Read Write 200 4 Read Write 400 5 Read Write 267 4 Read Write 400 5 Read Write 267 4 Read Write Chapter 4: Functional Description Block Description Total Latency Local Clock Time Cycles (ns) 18 151 120 175 11 105 20 120 105 100 ...

Page 35

... Chapter 4: Functional Description Block Description 1 The exact latency depends on your precise configuration. You should obtain precise latency from simulation, but this figure may vary in hardware because of the automatic calibration process. f Refer to the Latency section in chapter 1 of the Megafunction User Guide (ALTMEMPHY) ...

Page 36

... The encoder—encodes the 64-bit message to a 72-bit codeword ■ The decoder-corrector—decodes and corrects the 72-bit codeword if possible The ECC controller—controls multiple encoder and decoder-correctors, so that the ■ ECC can handle different bus widths. Also, it controls the following functions of ...

Page 37

... For more information on the ECC registers, refer to Description. The ECC can instantiate multiple encoders, each running in parallel, to encode any width of data words assuming they are integer multiples of 64. The ECC operates between the local (native or Avalon-MM interface) and the memory controller. ...

Page 38

... A partial write results in a read followed by write in the ECC controller, so latency depends on the time the controller takes to fetch the data from the particular address. DDR and DDR2 SDRAM High-Performance Controller User Guide Chapter 4: Functional Description Block Description © March 2009 Altera Corporation ...

Page 39

... Chapter 4: Functional Description Example Design Table 4–3 shows the relationship between burst lengths and rate. Table 4–3. Burst Lengths and Rates Local Burst Length Local Burst Length 2 For a local burst length of 2, the write latency increases by two clock cycles; the read latency increases by one clock cycle (including checking and correction) ...

Page 40

... MAX_ROW, MAX_BANK, and MAX_COL constants in the example driver source code, and the entire memory space can be tested by adjusting these values. You can skip this test by setting the test_seq_addr_on signal to logic zero. DDR and DDR2 SDRAM High-Performance Controller User Guide ...

Page 41

... The second set of write commands has only one byte enable bit asserted. The state machine then issues a read request to the same addresses and the data is verified. This test checks if the data mask pins are operating correctly. You can skip this test by setting the test_dm_pin_on signal to logic zero. ■ Address pin operation ...

Page 42

... DDR and DDR2 SDRAM High-Performance Controller User Guide shows write accesses with a controller in full-rate mode and Chapter 4: Functional Description Interfaces and Signals © March 2009 Altera Corporation ...

Page 43

... Chapter 4: Functional Description Interfaces and Signals Figure 4–5. Full Rate Write, Avalon-MM Interface [1] phy_clk Local Interface local_address 00 2 local_size local_ready local_burstbegin local_write_req local_read_req local_wdata AA BB local_be Controller - PHY Interface (Non-AFI) ddr_a ddr_ba ddr_cs_n DDR Command (1) NOP control_wdata_valid control_dqs_burst control_wdata control_be PHY - Memory Interface ...

Page 44

... The user logic requests the first write, by asserting the local_write_req signal, and the size and address for this write. In this example, the request is a burst of length the memory side) to chip select 1. The local_ready signal is asserted, which indicates that the controller has accepted this request, and the user logic can request another read or write in the following clock cycle ...

Page 45

... Chapter 4: Functional Description Interfaces and Signals Full Rate Write, Native Interface Mode—Non-Consecutive Write Figure 4–6 on page 4–18 using the Local Interface Protocol setting set to Native interface. The figure shows non-consecutive write-to-write requests, each of burst size 2 to sequential addresses. In full-rate mode, the controller allows you to use burst size achieve the highest throughput, you should use bursts of size 2, which correspond to a complete memory burst of 4 ...

Page 46

... Note to Figure 4–6: (1) DDR Command and Mem Command show the command that the command signals are issuing. DDR and DDR2 SDRAM High-Performance Controller User Guide [4] [5] [6] [7] [8] [9] 000 PCH ACT PCH Chapter 4: Functional Description Interfaces and Signals [10] [11] [12] [13 ...

Page 47

... Chapter 4: Functional Description Interfaces and Signals The following sequence corresponds with the numbered items page 4–18. 1. The user logic initiates the first write by asserting local_write_req signal, and the size and address for this write. In this example, the request is a burst length local address 0x000004 ...

Page 48

... DDR and DDR2 SDRAM High-Performance Controller User Guide External Memory PHY Interface Megafunction User Guide for more details of this interface. shows write accesses with a controller in half-rate mode and Chapter 4: Functional Description Interfaces and Signals © March 2009 Altera Corporation ...

Page 49

... Chapter 4: Functional Description Interfaces and Signals Figure 4–7. Half Rate Write, Avalon-MM Interface Mode [1] phy_clk Local Interface local_address 0000 0004 0008 local_size local_ready local_burstbegin local_write_req local_wdata_valid local_wdata AAAA BBBB CCCC DDDD EEEE local_be Controller - PHY Interface (Non-AFI) ddr_a ddr_ba ddr_cs_n DDR Command (1) ...

Page 50

... The user logic requests the first write, by asserting the local_write_req signal, and the size and address for this write. In this example, the request is a burst of length the memory side) to chip select 1. The local_ready signal is asserted, which indicates that the controller has accepted this request, and the user logic can request another read or write in the following clock cycle ...

Page 51

... Chapter 4: Functional Description Interfaces and Signals Figure 4–8. Half Rate Write, Native Interface Mode [1] [2] [3] phy_clk Local Interface local_address 00 01 local_size 1 local_ready local_write_req local_read_req local_wdata_req local_wdata BBAA local_be Controller - PHY Interface (Non-AFI) ddr_a ddr_ba ddr_cs_n DDR Command (1) control_wdata_valid control_dqs_burst control_wdata control_be ...

Page 52

... External Memory PHY Interface Megafunction for more details of this interface. Chapter 4: Functional Description Interfaces and Signals Figure 4–8 on <BBCCDDEE> <1010> <EE> <DD> <CC> <BB> <1> <0> <1> <1> © March 2009 Altera Corporation ...

Page 53

... Chapter 4: Functional Description Interfaces and Signals Full Rate Read, Avalon-MM Interface Mode Figure 4–9 shows three consecutive read requests of the same burst size. In full-rate mode, the controller allows you to use burst size achieve the highest throughput, you bursts of 2, which correspond to a complete memory burst of 4. ...

Page 54

... If there is ECC logic in the controller, there is one or three clock cycles of delay between the control_rdata and local_rdata buses. DDR and DDR2 SDRAM High-Performance Controller User Guide Chapter 4: Functional Description Interfaces and Signals External Memory PHY Interface Megafunction for more details of this interface. ...

Page 55

... Chapter 4: Functional Description Interfaces and Signals Half Rate Read, Native Interface Mode Figure 4–10 on page 4–27 size. In half-rate mode, the controller allows you to use burst size 1, which corresponds to a complete memory burst of 4. Figure 4–10. Half Rate Read, Native Interface Mode ...

Page 56

... DDR and DDR2 SDRAM High-Performance Controller User Guide External Memory PHY Interface Megafunction for more details of this interface. shows three consecutive read requests of the same burst Chapter 4: Functional Description Interfaces and Signals © March 2009 Altera Corporation ...

Page 57

... Chapter 4: Functional Description Interfaces and Signals Figure 4–11. Half Rate Read, Avalon-MM Interface Mode—Non-Consecutive Read [1] [2] phy_clk Local Interface 4 802 804 806 808 local_address local_size local_burstbegin local_read_req local_ready local_rdata_valid local_rdata Controller - PHY Interface (Non-AFI ddr_a ddr_ba ddr_cs_n 0 RD DDR Command (1) ...

Page 58

... DDR and DDR2 SDRAM High-Performance Controller User Guide Chapter 4: Functional Description External Memory PHY Interface Megafunction User Guide for more details of this interface. Interfaces and Signals Figure 4– ...

Page 59

... Chapter 4: Functional Description Interfaces and Signals 8. The controller returns the first read data to the user by asserting the local_rdata_valid signal when there is valid read data on the local_rdata bus. If Enable error correction and detection logic is disabled, there is no delay between the control_rdata and the local_rdata buses. If there is ECC logic in the controller, there is one or three clock cycles of delay between the control_rdata and local_rdata buses ...

Page 60

... NOP RD NOP WR NOP AABB 0FF 4 0000 8 0000 10 WR NOP RD NOP WR [4] [5] [12] [16] [17] [24] Chapter 4: Functional Description Interfaces and Signals [22] [6] [23] [19] 1 FFFF CCDD FFFF 3 0000 0 NOP [18] © March 2009 Altera Corporation ...

Page 61

... Chapter 4: Functional Description Interfaces and Signals The following sequence corresponds with the numbered items in page 4–32. 1. The user logic requests the first read by asserting the read request signal. In this example, the request is a burst length of 1. The local_ready signal is asserted, which indicates that the controller has accepted this request, and the user logic can request another read or write in the following clock cycle ...

Page 62

... DDR Command shows the command that the command signals are issuing. DDR and DDR2 SDRAM High-Performance Controller User Guide [2] [ 0400 0400 0000 0 PCH NOP ARF NOP Chapter 4: Functional Description Interfaces and Signals [ ARF ARF NOP © March 2009 Altera Corporation ...

Page 63

... Chapter 4: Functional Description Interfaces and Signals The following sequence corresponds with the numbered items in 1. The user logic asserts the refresh request signal to indicate to the controller that it should perform a refresh. The read and write requests signal do not need to be interrupted or paused in any way. If the user logic asserts refresh_req, the ...

Page 64

... DDR and DDR2 SDRAM High-Performance Controller User Guide (1) (2) (3) (1) (2) Specifications). You can assert it anytime, but once you have Chapter 4: Functional Description Interfaces and Signals (4) (5) (3) (4) © March 2009 Altera Corporation ...

Page 65

... Chapter 4: Functional Description Interfaces and Signals 1 If your MegaCore variation is configured to support local burst sizes greater than one, note that local_autopch is ignored unless you request a complete burst not possible to auto-precharge a partial burst to the memory. Signals Table 4–6 shows the clock and reset signals. ...

Page 66

... Should be connected to the ALT_OCT megafunction output parallelterminationcontrol. Input Allows the use of DLL in another ALTMEMPHY instance in this ALTMEMPHY instance. Connect the export port on the ALTMEMPHY instance with a DLL to the import port on the other ALTMEMPHY instance. Chapter 4: Functional Description Interfaces and Signals Description © March 2009 Altera Corporation ...

Page 67

... For multiple chip selects: width = chip bits + bank bits + row bits + column bits – the bank address is 2 bits wide, row is 13 bits wide and column is 10 bits wide, then the local address is 23 bits wide. To map local_address to ...

Page 68

... This option allows complete control over when refreshes are issued to the memory including ganging together multiple refresh commands. Refresh requests take priority over read and write requests unless they are already being processed. ...

Page 69

... Chapter 4: Functional Description Interfaces and Signals Table 4–7. Local Interface Signals (Part Signal Name Direction Input local_write_req Output local_init_done Output local_rdata[] Output local_rdata_error Output local_rdata_valid Output local_ready Output local_refresh_ack Output local_wdata_req Input local_autopch_req © March 2009 Altera Corporation Description Write request signal. ...

Page 70

... Memory clock enable signals. Memory chip select signals. Memory data mask signal, which masks individual bytes during writes. Memory on-die termination control signal (DDR2 SDRAM only). Memory row address strobe signal. Chapter 4: Functional Description Interfaces and Signals © March 2009 Altera Corporation ...

Page 71

... Chapter 4: Functional Description Interfaces and Signals Table 4–8. DDR and DDR2 SDRAM Interface Signals (Part Signal Name Direction Output mem_we_n Note to Table 4–8: (1) The mem_clk signals are output only signals from the FPGA. However, in the Quartus II software they must be defined as bidirectional (INOUT) I/Os to support the mimic path structure that the ALTMEMPHY megafunction uses. Table 4– ...

Page 72

... DDR and DDR2 SDRAM High-Performance Controller User Guide Chapter 4: Functional Description Interfaces and Signals © March 2009 Altera Corporation ...

Page 73

... The design example in this chapter shows you how to use a DDR2 SDRAM high- performance controller in non-AFI mode with a Cyclone III device, and half-rate implementation on a Windows-based system. The principles in this design example are the same for any other mode of the Altera DDR and DDR2 SDRAM high- performance ALTMEMPHY-based memory controllers ...

Page 74

... ALTMEMPHY megafunction. This example allows you to quickly create a working design. The MegaCore function uses this example design in a testbench by connecting generic memory model and providing the required clock_source and global_reset_n stimulus automatically. Testbench Description The example design consists of the following blocks or components: ALTMEMPHY megafunction ■ memory controller ■ ...

Page 75

... On the File menu, click Change Directory. 3. Select <your project name>/simulation/modelsim and click OK the Tools menu, click Execute Macro. 5. Select <your project name>_run_msim_rtl_verilog.do and click OK. © March 2009 Altera Corporation AN 380: Test DDR or DDR2 SDRAM Interfaces on Driver. AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II Devices ...

Page 76

... ModelSim-AE includes all Altera device libraries .do script for ModelSim-AE does not compile these libraries. NativeLink includes the relevant libraries for other simulators. f Refer to Altera-supported RTL simulation tools. The Testbench Stages Before the user logic (example driver) can read or write to the local interface, the external SDRAM must first be initialized and calibrated ...

Page 77

... Figure 5–2, the expected waveform view of the initialization phase is directly following the NOP of 200 µs. Steps is complete by the second yellow cursor. Additional signals are added to simplify debugging. © March 2009 Altera Corporation are expanded to increase detail. Initialization DDR and DDR2 SDRAM High-Performance Controller User Guide ...

Page 78

Figure 5–2. Simulation Initialization Phase ...

Page 79

... The example testbench stops when either test_complete is asserted or when 200,000 mem_clk cycles after the t © March 2009 Altera Corporation (Native interface only) (Avalon-MM interface only) External Memory PHY Interface (ALTMEMPHY). ...

Page 80

... The data on the read data bus should match that on the write data bus during the read process. DDR and DDR2 SDRAM High-Performance Controller User Guide Chapter 5: Example Design Walkthrough shows the series of writes followed by reads on both the local The Testbench Stages © March 2009 Altera Corporation ...

Page 81

Figure 5–3. Functional Memory Use Stage ...

Page 82

... DDR and DDR2 SDRAM High-Performance Controller User Guide Chapter 5: Example Design Walkthrough The Testbench Stages © March 2009 Altera Corporation ...

Page 83

... Current double-bit error 04 count Last or first single-bit error 05 error address Last or first double-bit error 06 error address © March 2009 Altera Corporation A. ECC Register Description Size (Bits) Attribute Default 32 R/W 0000000F This register contains all commands for the ECC functioning. 32 R/W ...

Page 84

... RO 00000000 This status register stores the last double-bit error error data word. As the data word is an Nth multiple of 64, the data word is stored deep, 32-bit wide FIFO buffer with the least significant 32-bit sub word stored first. It can be cleared individually by using the control word clear ...

Page 85

... When 1, single-bit error maximum threshold exceeded. Maximum double-bit error When 1, double-bit error maximum threshold exceeded. Double-bit error during read- When 1, double-bit error occurred during a read modify-write modify write condition. (partial write). Reserved Reserved. DDR and DDR2 SDRAM High-Performance Controller User Guide A–3 Description Description ...

Page 86

... Interrupt When 0, no single-bit error; when 1, single-bit error occurred in this 64-bit part. Reserved Reserved. Name Cause of Interrupt When 0, no double-bit error; when 1, double- bit error occurred in this 64-bit part. Reserved Reserved. Register Bits Description Description Description © March 2009 Altera Corporation ...

Page 87

... Updated new read and write waveforms. ■ Updated section on Example Driver. ■ Added new section on DDR/DDR2 SDRAM High-Performance Controller Architecture. ■ Added new section on Simulating With Other Simulators - VHDL/Verilog HDL IP ■ Functional Simulation. May 2008 8.0 Updated new read and write waveforms. ...

Page 88

... Active-low signals are denoted by suffix n. For example, resetn. Indicates command line commands and anything that must be typed exactly as it appears. For example, c:\qdesigns\tutorial\chiptrip.gdf. Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword SUBDESIGN), and logic function names (for example, TRI) ...