IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 97
IPR-PCIE/1
Manufacturer Part Number
IPR-PCIE/1
Description
IP CORE Renewal Of IP-PCIE/1
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCIE/1
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Express Compiler, x1 Link Width
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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Specifications
Figure 3–21. 64-Bit Memory Read Request Waveform
Altera Corporation
December 2006
Descriptor
Signals
Signals
Data
tx_desc[127:0]
tx_data[63:32]
tx_data[31:0]
tx_ack
tx_req
tx_ws
tx_err
tx_dfr
tx_dv
Transmit Request Can Remain Asserted Between Transaction Layer
Packets
In this example, the application transmits a 64-bit memory read
transaction followed by a 64-bit memory write transaction. Address bit 2
is set to 0. See
In clock cycle 4, tx_req is not deasserted between transaction layer
packets.
In clock cycle 5, the second transaction layer packet is not immediately
acknowledged because of additional overhead associated with a 64-bit
address, such as a separate number and an LCRC. This situation leads to
an extra clock cycle between two consecutive transaction layer packets.
1
X
X
PCI Express Compiler Version 6.1
2
MEMRD64
3
Figure
4
MEMWR64
5
3–21.
6
DW1
DW0
Clock Cycles
7
8
DW3
DW2
9
DW5
DW4
10
PCI Express Compiler User Guide
DW6
DW7
11
12
13
14
X
X
15
3–59
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