IR1153SPBF International Rectifier, IR1153SPBF Datasheet - Page 11

IC PFC ONE CYCLE CONTROL 8SOIC

IR1153SPBF

Manufacturer Part Number
IR1153SPBF
Description
IC PFC ONE CYCLE CONTROL 8SOIC
Manufacturer
International Rectifier
Datasheet

Specifications of IR1153SPBF

Mode
Continuous Conduction (CCM)
Frequency - Switching
18.3kHz ~ 25kHz
Current - Startup
26µA
Voltage - Supply
14 V ~ 17 V
Operating Temperature
-25°C ~ 125°C
Mounting Type
*
Package / Case
*
Startup Current
26µA
Operating Supply Current
7mA
Duty Cycle (%)
99%
Frequency
22.2kHz
Digital Ic Case Style
SOIC
No. Of Pins
8
Operating Temperature Range
-25°C To +125°C
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
Supply Voltage Range
14V To 17V
Package
8-lead SOIC
Circuit
PFC IC
Vcc Range (v)
14V-17V
Out Peak Current (a)
+/- 0.75
Switching Frequency (khz)
22.2
Environment
Industrial
Over-voltage Protection
Yes
Brown-out Protection
Yes
Pbf
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
www.irf.com
IR1153 Modes of operation
Referenced to States & Transition Diagram
UVLO/Sleep Mode: The IC is in the UVLO/Sleep
mode when VCC pin voltage is below V
start-up or when VCC pin voltage drops below
V
pin voltage is below V
mode is accessible from any other state of
operation. This mode can be actively invoked by
pulling the OVP/EN pin below V
pin voltage is above V
state, the gate drive circuit is inactive, most of the
internal circuitry is unbiased and the IC draws a
quiescent current of I
75uA. Also, the internal logic of the IC ensures
that whenever the Sleep mode is actively invoked,
the COMP pin is actively discharged below
V
mode, in order to facilitate soft-start upon
resumption of operation.
Stand-by Mode: The IC is placed in Stand-by
mode whenever an Open-loop and/or a Brown-out
situation is detected. A Brown-out situation is
sensed when BOP pin voltage is less than
V
pin voltage drops below V
Open-loop situation is sensed anytime VFB pin
voltage is less than V
biased in the Stand-by Mode, but the gate is
inactive and the IC draws a few mA of current.
This state is accessible from any other state of
operation of the IC. COMP pin is actively
discharged to below V
state is entered from normal operation in order to
facilitate soft-start upon resumption of operation.
Soft Start Mode: During system start-up, the soft-
start mode is activated once the VCC voltage has
exceeded V
exceeded V
exceeded V
than V
greater than V
to commence operation. The soft start time is the
time required for the VCOMP voltage to charge
through its entire dynamic range i.e. through
V
dependent upon the component values selected
for compensation of the voltage loop on the
COMP pin. To an extent, keeping in mind the
voltage feedback loop considerations, the soft-
system start time is programmable.
CC,UVLO
COMP,START
BOP(EN)
COMP,EFF
COMP,START
during normal operation or when OVP/EN
prior to system start-up and when BOP
. As a result, the soft-start time is
threshold prior to entering the sleep
BOP(EN)
CC,ON
OLP
COMP,START
, the VFB pin voltage has
i.e. a pre-bias on COMP pin
and BOP pin voltage has
and VCOMP voltage is less
OLP
SLEEP
CC,ON
SLEEP
COMP,START
threshold will not allow IC
. All internal circuitry is
BOP
. In the UVLO/Sleep
.
which is less than
after start-up. An
SLEEP
The UVLO/Sleep
whenever this
even if VCC
CC,ON
at
11
As VCOMP voltage rises gradually, the IC allows
a higher and higher RMS current into the PFC
converter. This controlled increase of the input
current amplitude contributes to reducing system
component stress during start-up.
Normal Mode: The IC enters the normal
operating mode once the soft start transition has
been completed (for all practical purposes there is
essentially no difference between the soft-start
and normal modes). At this point the gate drive is
switching and all protection functions of the IC are
active. If, from the normal mode, the IC is pushed
into either a Stand-by mode or UVLO/Sleep mode
then COMP pin is actively discharged below
V
upon resumption of operation.
OVP Mode: The IC enters OVP mode whenever
an overvoltage condition is detected. A system
overvoltage
OVP/EN pin voltage exceeds V
When this happens the IC immediately disables
the gate drive and holds it in that state. The gate
drive is re-enabled only when OVP/EN pin
voltages are less than V
state is accessible from both the soft start and
normal modes of operation.
IPK LIMIT Mode: The IC enters IPK LIMIT mode
whenever the magnitude of ISNS pin voltage
exceeds the V
cycle peak overcurrent protection. When this
happens, the IC immediately disables the gate
drive and holds it in that state. Gate drive is re-
enabled when magnitude of ISNS pin voltage
drops below V
accessible from both the soft start and normal
modes of operation.
COMP,START
and system will go through soft-start
ISNS(PK)
condition
ISNS(PK)
threshold triggering cycle-by-
threshold. This state is
is
OVP(RST)
© 2011 International Rectifier
recognized
threshold. This
OVP
IR1153S
threshold.
when

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