71M6512-DB Maxim Integrated Products, 71M6512-DB Datasheet - Page 126
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71M6512-DB
Manufacturer Part Number
71M6512-DB
Description
Power Management Modules & Development Tools 71M6512 DEMO BOARD 71M6512 DEMO BOARD
Manufacturer
Maxim Integrated Products
Datasheet
1.71M6521DE-DB.pdf
(138 pages)
- Current page: 126 of 138
- Download datasheet (2Mb)
The watchdog timer is a 16-bit counter that is incremented once every 24 or 384 clock cycles. After an external reset,
the watchdog timer is disabled and all registers are set to zero.
The watchdog consists of a 16-bit counter (wdt), a reload register (WDTREL), prescalers (by 2 and by 16), and control
logic.
During an active internal reset signal, the programmer can start the watchdog later. It will occur when the SWD signal
becomes active. Once the watchdog is started, it cannot be stopped unless the internal reset signal becomes active.
When the WDT registers enters the state 0x7CFF , an asynchronous WDTS signal will become active. The signal
WDTS sets bit 6 in the IP0 register and requests a reset state. WDTS is cleared either by the reset signal or changing
the state of the WDT timer.
Revision 1.7
6.3.4 Software Watchdog Timer
6.3.4.1
fclk/12
swdt
/
/
swd
16
wdt
2
Software Watchdog Timer structure
WD Timer Start Procedure
© Copyright 2005-2007 TERIDIAN Semiconductor Corporation
0
Figure 6-3: Watchdog Block Diagram
Control
logic
wdtl
TERIDIAN Proprietary
7
7 6
8
wdtrel
wdth
71M652X Software User’s Guide
14
0
wdts
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