LFE3-95E-PCIE-DKN Lattice, LFE3-95E-PCIE-DKN Datasheet - Page 20

• Manufacturer Part Number: LFE3-95E-PCIE-DKN
• Description: MCU, MPU & DSP Development Tools LatticeECP3 PCI Express Dev Kit
• Manufacturer: Lattice

Specifications of LFE3-95E-PCIE-DKN

• Processor To Be Evaluated: LFE3-95EA-x
• Processor Series: LatticeECP3
• Interface Type: SPI
• Operating Supply Voltage: 1.2 V to 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Edge Clock Sources
Edge clock resources can be driven from a variety of sources at the same edge. Edge clock resources can be
driven from adjacent edge clock PIOs, primary clock PIOs, PLLs, DLLs, Slave Delay and clock dividers as shown in
Figure 2-19.
Figure 2-19. Edge Clock Sources
Edge Clock Routing
LatticeECP3 devices have a number of high-speed edge clocks that are intended for use with the PIOs in the
implementation of high-speed interfaces. There are six edge clocks per device: two edge clocks on each of the top,
left, and right edges. Different PLL and DLL outputs are routed to the two muxes on the left and right sides of the
device. In addition, the CLKINDEL signal (generated from the DLL Slave Delay Line block) is routed to all the edge
clock muxes on the left and right sides of the device. Figure 2-20 shows the selection muxes for these clocks.
From Routing
From Routing
Notes:
1. Clock inputs can be configured in differential or single ended mode.
2. The two DLLs can also drive the two top edge clocks.
3. The top left and top right PLL can also drive the two top edge clocks.
Sources for left edge clocks
Input
Input
DLL
PLL
Clock
Clock
Input
Input
Slave Delay
PLL
DLL
Routing
From
Six Edge Clocks (ECLK)
Two Clocks per Edge
Clock Input
2-17
Clock Input
Routing
From
Sources for top
edge clocks
LatticeECP3 Family Data Sheet
Sources for right edge clocks
Slave Delay
DLL
PLL
Architecture
From Routing
From Routing
Clock
Clock
Input
Input
Input
Input
DLL
PLL