Core429-DEV-KIT Actel, Core429-DEV-KIT Datasheet
Core429-DEV-KIT
Specifications of Core429-DEV-KIT
Related parts for Core429-DEV-KIT
Core429-DEV-KIT Summary of contents
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... Implemented in an APA600 Device – Controlled Via an External Terminal Using Core8051 and RS232 Links • Includes Line Driver and Receiver Components Synthesis and Simulation Support • Directly Supported within the Actel Libero IDE • Synthesis: – Synplicity® TM – Exemplar ® ...
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... High +5 B Null 0 –5 Low 1 "Functional Figure 2 • Figure 3 on page 3 data. Each ARINC word contains five fields: • Parity v5.0 Rx I/F Glue CPU Logic Interface Tx I/F CoreARINC429 Actel FPGA Typical Core429 System—One Tx and One Rx for commercial and ARINC Standard ...
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... The order of the bits transmitted on the ARINC bus is as follows 10, 11, 12, 13 … 32. Core429 Device Requirements Core429 can be implemented in several Actel FPGA devices. utilization figures using standard synthesis tools for different Core429 configurations. size is set to 64 and FIFO depth is set to 64. Table 1 • Device Utilization for One Tx Module ...
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... Axcelerator 955 RTAX-S 1,062 Core429 clock rate can be programmed 10, 16 MHz. All the Actel families listed above easily meet the required performance. Core429 I/O requirements depend on the system requirements and the external interfaces. If the core and memory blocks are implemented within the FPGA and ...
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... FIFO for receiver # 2, and 64-words-deep FIFO for transmitter, then the number of memory blocks = INT (64/128) + (INT (32/512) + INT (32/128)) + (INT (64/512) + INT (64/128)) Core429 Overview Core429 provides a complete and flexible interface to a microprocessor and an ARINC 429 data bus. Connection to an ARINC 429 data bus requires additional line drivers and line receivers ...
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... Figure 4 • Core429 Rx Block Diagram The Rx block is responsible for recovering the clock from the input serial data and performs serial-to-parallel conversion and gap/parity check on the incoming data. It also interfaces with the CPU. The Rx module contains two 8-bit registers. One is used for control function and the other is used for status ...
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... Figure 5 • Core429 Tx Block Diagram The Tx module converts the 32-bit parallel data from the TX FIFO to serial data. It also inserts the parity bit into the ARINC data when parity is enabled. The CPU interface is used to fill the FIFO with ARINC data. The TX FIFO can hold up to 512 ARINC words of data ...
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... ARINC 429 Bus Interface Core Parameters Core429 has several top-level Verilog parameters (VHDL generics) that are used to select the number of channels and FIFO sizes of the core that is implemented. Using these parameters allows the size of the core to be reduced when all the channels are not required. ...
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... CPU Interface The CPU interface allows access to the Core429 internal registers, FIFO, and internal memory. This interface is synchronous to the clock. Table 10 • CPU Interface Signals Name cpu_ren cpu_wen cpu_add [8:0] cpu_din [CPU_DATA_WIDTH-1:0] cpu_dout [CPU_DATA_WIDTH-1:0] ...
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... ARINC 429 Bus Interface Legacy Interface The Legacy interface allows access to the Core429 internal registers, FIFO, and internal memory. This interface is synchronous to the clock. The Tx module contains two 8-bit registers. One is used for control function and the other is used for status. ...
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The address bit 4 is used to determine Rx/Tx as follows: 0 – – Tx The address bits and 8 are used for decoding the 16 channels as follows: 0000 – Channel0 Table 12 • ...
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ARINC 429 Bus Interface Table 16 • Rx Label Memory Register Bit Function 7:0 Label Tx Registers Following is a detailed definition of cpu_add [3:2] decoding and an explanation of the Data Register, Pattern RAM, Control Register, and Status Register. ...
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Label Memory Operation The label memory is implemented using an internal memory block. The read address and write address are generated by internal counters. The read and write address counters can be reset by setting bit 7 of the +1 ...
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... ARINC 429 Bus Interface Control Register Core429 contains a 16-bit control register, which is used to configure the Rx and Tx channels. The control register bits are loaded from the databus when CTRL_n is low. The control register contents are output on the databus when RSEL is high and STR_n is low. Each bit of the control register description is explained in Table 20 • ...
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... Status Register Core429 contains a 16-bit status register which can be read to determine the status of the ARINC receivers, data FIFOs, and transmitter. The contents of the status register are output on the databus when RSEL is low and STR is low. Each bit of the control register description is explained in Table 21 • ...
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... ARINC 429 Bus Interface CPU Interface Timing for Default Mode The CPU interface signals are synchronized to the Core429 master clock. the waveforms for the CPU interface. clk cpu_ren cpu_add[8:0] cpu_dout[31:0] cpu_wait Note: cpu_ren should be deasserted on the next clock cycle after cpu_wait is deasserted. The read data is available one cycle after cpu_ren is sampled. Figure 7 • ...
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... Loopback tests Using the supplied user testbench as a guide, the user can easily customize the verification of the core by adding or removing tests. Testbench The CPU model sets up Core429 via the CPU interface . and loads the transmit data The transmit data will be Write ...
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... Connect transmit channel 0 output to receive channel 3 input. Development System A complete ARINC 429 development system is also available, Actel part number "Core429-DEV-KIT". The development system uses an external terminal (PC) using a serial UART link to control Core429 with four Rx and four Tx channels implemented in a single ProASIC APA600 FPGA ...
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... Netlist for unlimited use on Actel devices SR RTL for single use on Actel devices AR RTL for unlimited use on Actel devices UR RTL for use not restricted to Actel devices The Evaluation board can also be ordered using the part number "Core429-DEV-KIT". APA600 FPGA Core 429 4Tx and 4Tx Keypad ADC and ...
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... Figure 12. The wave forms were modified in and notes were added to each figure was updated to modify the selectable data rate on each channel. and "ARINC 429 Overview" section "Core429 Device Requirements" was added. was updated. was added. Table 9 were moved to Table 8. Table 9 " ...
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... The title of Table 4 v3.1 The "Supported Families" section The "Core429 Device Requirements" section v3.0 The "Core Deliverables" section Table 5 is new. Table 9 was updated. Figure 9 was updated. v2.0 The "Core429 Device Requirements" Table 1 was updated. Table 2 was updated. Table 3 was updated. ...
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