LS-X2280-BASE-PC-N Lattice, LS-X2280-BASE-PC-N Datasheet

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LS-X2280-BASE-PC-N

Manufacturer Part Number
LS-X2280-BASE-PC-N
Description
MCU, MPU & DSP Development Tools ispLEVER Base MachXO -2280 Std Dev Kit
Manufacturer
Lattice
Datasheet

Specifications of LS-X2280-BASE-PC-N

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
MachXO™ Standard Evaluation Board - Revisions 001 & 002
User’s Guide
March 2008
Revision: EB21_01.6

Related parts for LS-X2280-BASE-PC-N

LS-X2280-BASE-PC-N Summary of contents

Page 1

MachXO™ Standard Evaluation Board - Revisions 001 & 002 User’s Guide March 2008 Revision: EB21_01.6 ...

Page 2

... The board provides fixed 1.2V and 3.3V power rails and a single adjustable voltage that ranges from 1.2V to 3.3V possible to use external power supplies to override the fixed output levels if desired. The voltage supplied to the MachXO core is selectable. The core voltage is changed by moving a single current sense resistor. ...

Page 3

... Setting all of the 8-bit input switches to OFF reverses the direction of the count. If the switches are not all ON or all OFF, the LEDs for the switches that are ON will light up. Additionally, other I/Os on the MachXO device are also toggled using the internal counter outputs. See the source code and preference file available on- line for more information. ...

Page 4

... Due west of the fuse blocks are more banana plug connectors. These connectors provide an alternate means for applying DC voltage levels to the board. To apply voltages not supplied by the on-board power section, first remove the appropriate fuse from the fuse holder . Then connect an alternate DC supply to the banana plug connector associated with that fuse ...

Page 5

... A single resistor can be moved to permit 1.2V, 3.3V Table 2. MachXO Core Voltage Selection The remaining current sense resistors permit the measurement of the V Table 3. MachXO I/O Voltage Rails Four V banks are available on the MachXO Standard Evaluation board. Three of the four I/O banks can be CCIO selected ...

Page 6

... Adjacent, westward diode D11 (green). This is a LED tied to a general purpose I/O on the MachXO. This LED signals that the MachXO is done being programmed. However, it can be used to signal any status desired. Evaluation bitstreams will tie output pin T6 to drive low, turning D11 on. ...

Page 7

... For example, starting in the upper-left of Grid 1; location A2 and A3 are unconnected, location A4 is connected to the MachXO I/O pin A4, etc. Both grids also have a series of pull-up/pull-down/inline resistors connected to the through holes. Figure 4 shows how these resistors may be arrayed around the prototype area. MachXO Standard Evaluation Board Revisions 001 & ...

Page 8

... If a series resistor with a non-zero value is needed, this short-circuit trace can be removed. The pull-up resistors within this grid can be configured to be pulled to one of the three available voltage rails on the board. Table 6 shows how the voltage rails are assigned. Refer to the schematic to determine which resistor pads connect to which MachXO I/O ...

Page 9

... Lattice Semiconductor Figure 5. Prototype Grid 4 Short-circuit Prototype Grid 5 : The last of the prototype grid is designed for use with an LCD display. U3 can be populated by a Lumex LCD-S501C39TR five-element, seven-segement LCD display. When this display is populated mounted on the rows between U3 and JP23/JP24. JP23 and JP24 can then be populated with general-purpose headers. ...

Page 10

... LED Displays On the south edge of the board is a set of eight green 0603 form factor LEDs. These LEDs are connected to I/O pins dedicated to driving the LEDs. Table 7 shows which MachXO I/O controls each LED. The LEDs illuminate when the corresponding I/O is driven to V Table 7 ...

Page 11

... JP9 Pin 1 Note: XU2 pin 9 is routed to one of the two PLLs included on larger MachXO devices. These MachXO PLLs are not available on the MachXO640 device. XU2 pin 9 provides input to the PLL_T input pin M5. JP2 and JP3 are routed to the second set of PLL input pins on the MachXO device. On the MachXO640, these input pins are general purpose I/O ...

Page 12

... Figure 7. Figure 7. ispClock Configuration Headers JP11 - JP17 configure all of the ispClock features. Table 11 shows which jumper block controls which ispClock pin. Refer to the ispClock5610 Family Data Sheet to understand what function each pin performs. Table 11. ispClock5610 Clock Source Jumper Block The ispClock has the ability to be programmed with four separate profi ...

Page 13

... I/O pins are routed to the Mictor connector. Ordering Information Description MachXO 2280C Evaluation Board - Standard MachXO 640C Evaluation Board - Standard ispLEVER Base with MachXO 2280 Standard Development Kit LS-X2280-BASE-PC-N Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: techsupport@latticesemi ...

Page 14

... Lattice Semiconductor Appendix A. PCB Schematic Figure 8. MachXO Control and Programming Interfaces MachXO Standard Evaluation Board Revisions 001 & 002 User’s Guide 14 ...

Page 15

... Lattice Semiconductor Figure 9. MachXO I/O Connections MachXO Standard Evaluation Board Revisions 001 & 002 User’s Guide PT5B/PT6F/PT9B/CLK0 D7 PT5A/PT6E/PT9A D8 15 PB5D/PB6F/PB9B P8 PB5C/PB6E/PB9A P7 ...

Page 16

... Lattice Semiconductor Figure 10. Power Section PGND Vin 16 SGND MachXO Standard Evaluation Board Revisions 001 & 002 User’s Guide ...

Page 17

... Lattice Semiconductor Figure 11. Miscellaneous Interfaces MachXO Standard Evaluation Board Revisions 001 & 002 User’s Guide GND_4 43 GND_3 42 GND_2 41 GND_1 40 GND_0 ...

Page 18

... Lattice Semiconductor Figure 12. ispClock5610 Connections MachXO Standard Evaluation Board Revisions 001 & 002 User’s Guide 1 1 ROUTING ROUTING AND AND DIVIDERS DIVIDERS OUTPUT OUTPUT GNDD_4 17 GNDD_3 16 GNDD_2 15 GNDD_1 48 GNDD_0 23 GNDA 14 VCCA 13 TEST2 45 VCCD_1 33 TEST1 46 VCCD_0 24 1 VCC 14 GND 7 18 ...

Page 19

... Lattice Semiconductor Figure 13. LED and LCD Connections MachXO Standard Evaluation Board Revisions 001 & 002 User’s Guide LIN36 LIN35 LIN37 LIN34 LIN38 23 18 LIN33 LIN28 LIN32 DP4 LIN29 LIN27 LIN30 LIN26 LIN31 LIN25 LIN20 LIN24 DP3 LIN21 LIN19 LIN22 LIN18 ...

Page 20

... Lattice Semiconductor Figure 14. Miscellaneous MachXO Standard Evaluation Board Revisions 001 & 002 User’s Guide 20 ...

Page 21

... Lattice Semiconductor Figure 15. Prototype Area MachXO Standard Evaluation Board Revisions 001 & 002 User’s Guide 21 ...

Page 22

... Lattice Semiconductor Figure 16. Prototype Area (Cont.) MachXO Standard Evaluation Board Revisions 001 & 002 User’s Guide 22 ...

Page 23

... Lattice Semiconductor Figure 17. Prototype Area (Cont.) MachXO Standard Evaluation Board Revisions 001 & 002 User’s Guide 23 ...

Page 24

... Lattice Semiconductor Figure 18. Prototype Area (Cont.) MachXO Standard Evaluation Board Revisions 001 & 002 User’s Guide 24 ...

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