SMAX-624CG-ACTEL Actel, SMAX-624CG-ACTEL Datasheet - Page 27

no-image

SMAX-624CG-ACTEL

Manufacturer Part Number
SMAX-624CG-ACTEL
Description
Programming Socket Adapters & Emulators SILICON SCULPTOR ADAPTER MODULE
Manufacturer
Actel

Specifications of SMAX-624CG-ACTEL

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Register Cell Timing Characteristics
Figure 1-17 • Flip-Flops
Timing Characteristics
Timing characteristics for SX devices fall into three
categories: family-dependent, device-dependent, and
design-dependent.
characteristics are common to all SX family members.
Internal routing delays are device-dependent. Design
dependency means actual delays are not determined
until after placement and routing of the user’s design is
complete. Delay values may then be determined by using
the DirectTime Analyzer utility or performing simulation
with post-layout delays.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most time-
critical paths. Critical nets are determined by net
property assignment prior to placement and routing. Up
to 6% of the nets in a design may be designated as
critical, while 90% of the nets in a design are typical.
PRESET
CLK
CLR
D
Q
The
t
input
SUD
and
output
D
(positive edge triggered)
CLK
t
HPWH'
RPWH
PRESET
buffer
CLR
t
HD
t
RCO
v3.2
Q
Long Tracks
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows,
columns, or modules. Long tracks employ three and
sometimes five antifuse connections. This increases
capacitance and resistance, resulting in longer net delays
for macros connected to long tracks. Typically up to 6
percent of nets in a fully utilized device require long
tracks. Long tracks contribute approximately 4 ns to 8.4
ns delay. This additional delay is represented statistically
in higher fanout (FO = 24) routing delays in the
datasheet specifications section.
Timing Derating
SX devices are manufactured in a CMOS process.
Therefore, device performance varies according to
temperature, voltage, and process variations. Minimum
timing parameters reflect maximum operating voltage,
minimum
processing.
minimum
temperature, and worst-case processing.
t
HPWL
RPWL
t
t
WASYN
CLR
'
operating
operating
Maximum
t
PRESET
t
HP
voltage,
temperature,
timing
maximum
parameters
SX Family FPGAs
and
operating
best-case
reflect
1-23

Related parts for SMAX-624CG-ACTEL