5M2210ZF256C5N Altera, 5M2210ZF256C5N Datasheet - Page 65
5M2210ZF256C5N
Manufacturer Part Number
5M2210ZF256C5N
Description
ALTERA
Manufacturer
Altera
Series
MAX Vr
Datasheets
1.DK-DEV-5M570ZN.pdf
(30 pages)
2.DK-DEV-5M570ZN.pdf
(164 pages)
3.DK-DSP-3SL150N.pdf
(80 pages)
4.5M240ZT100C5N.pdf
(72 pages)
Specifications of 5M2210ZF256C5N
Cpld Type
FLASH
No. Of Macrocells
1700
No. Of I/o's
271
Propagation Delay
7.5ns
Global Clock Setup Time
4.6ns
Frequency
201.1MHz
Supply Voltage Range
1.71V To 1.89V
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.0ns
Voltage Supply - Internal
1.71 V ~ 1.89 V
Number Of Logic Elements/blocks
2210
Number Of Macrocells
1700
Number Of Gates
-
Number Of I /o
203
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-LBGA
Rohs Compliant
Yes
Lead Free Status / Rohs Status
Vendor undefined / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
5M2210ZF256C5N
Manufacturer:
INTEL22
Quantity:
502
Part Number:
5M2210ZF256C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 3: DC and Switching Characteristics for MAX V Devices
Timing Model and Specifications
Table 3–32. External Timing Input Delay Adders for MAX V Devices
Table 3–33. External Timing Input Delay t
May 2011 Altera Corporation
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL /
LVCMOS
1.8-V LVTTL /
LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
3.3-V PCI
3.3-V LVTTL
External Timing I/O Delay Adders
I/O Standard
I/O Standard
Without Schmitt
Trigger
With Schmitt
Trigger
Without Schmitt
Trigger
With Schmitt
Trigger
Without Schmitt
Trigger
With Schmitt
Trigger
Without Schmitt
Trigger
Without Schmitt
Trigger
Without Schmitt
Trigger
Without Schmitt
Trigger
Without Schmitt
Trigger
With Schmitt
Trigger
The I/O delay timing parameters for the I/O standard input and output adders and
the input delays are specified by speed grade, independent of device density.
Table 3–32
pins for all packages. If you select an I/O standard other than 3.3-V LVTTL, add the
input delay adder to the external t
page 3–20
with 16 mA drive strength and fast slew rate, add the output delay adder to the
external t
CO
through
through
and t
Min
Min
—
—
—
—
—
—
—
—
—
—
—
—
GLOB
5M40Z/ 5M80Z/ 5M160Z/
5M40Z/ 5M80Z/ 5M160Z/
PD
C4
C4
Table
Table 3–36 on page 3–25
listed in
Adders for GCLK Pins for MAX V Devices (Part 1 of 2)
5M240Z/ 5M570Z
5M240Z/ 5M570Z
1,055
Max
Max
387
387
429
378
681
387
42
0
0
0
0
3–31. If you select an I/O standard other than 3.3-V LVTTL
Table 3–26 on page 3–20
Min
Min
—
—
—
—
—
—
—
—
—
—
—
—
C5, I5
C5, I5
SU
timing parameters listed in
1,010
Max
Max
442
442
483
368
658
442
42
0
0
0
0
list the adder delays associated with I/O
Min
Min
—
—
—
—
—
—
—
—
—
—
—
—
C4
C4
through
5M1270Z/ 5M2210Z
5M1270Z/ 5M2210Z
1,334
2,324
Max
Max
480
480
246
787
695
400
0
0
0
0
Table
Table 3–26 on
Min
Min
—
—
—
—
—
—
—
—
—
—
—
—
MAX V Device Handbook
3–31.
C5, I5
C5, I5
1,642
2,860
Max
Max
591
591
303
968
855
493
0
0
0
0
Unit
Unit
3–23
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps