EVAL-ADAU1761Z Analog Devices Inc, EVAL-ADAU1761Z Datasheet - Page 65

• Manufacturer Part Number: EVAL-ADAU1761Z
• Description: Eval Board For ADAU1761
• Manufacturer: Analog Devices Inc
• Series: SigmaDSP®r

Specifications of EVAL-ADAU1761Z

• Main Purpose: Audio, CODEC
• Embedded: Yes, DSP
• Utilized Ic / Part: ADAU1761
• Primary Attributes: Stereo, 24-Bit, 8 ~ 96 kHz Sampling Rate, GUI Tool
• Secondary Attributes: I²C and GPIO Interfaces, 2 Differential and 1 Stereo Single-Ended Analog Inputs and Outputs
• Silicon Manufacturer: Analog Devices
• Core Architecture: SigmaDSP
• Silicon Core Number: ADAU1761
• Silicon Family Name: SigmaDSP
• Application Sub Type: Audio
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

R17: Converter Control 0, 16,407 (0x4017)
Bit 7
Reserved
Table 51. Converter Control 0 Register
Bits
[6:5]
4
3
[2:0]
R18: Converter Control 1, 16,408 (0x4018)
Bit 7
Table 52. Converter Control 1 Register
Bits
[1:0]
Bit Name
DAPAIR[1:0]
DAOSR
ADOSR
CONVSR[2:0]
Bit Name
ADPAIR[1:0]
Bit 6
Bit 6
On-chip DAC serial data selection in TDM 4 or TDM 8 mode.
On-chip ADC serial data selection in TDM 4 or TDM 8 mode.
Description
Setting
00
01
10
11
DAC oversampling ratio. This bit cannot be set for 64× when CONVSR[2:0] is set to 96 kHz.
0 = 128× (default).
1 = 64×.
ADC oversampling ratio. This bit cannot be set for 64× when CONVSR[2:0] is set to 96 kHz.
0 = 128× (default).
1 = 64×.
Converter sampling rate. The ADCs and DACs operate at the sampling rate set in this register. The converter rate
selected is a ratio of the base sampling rate, f
of the core clock.
Setting
000
001
010
011
100
101
110
111
Description
Setting
00
01
10
11
DAPAIR[1:0]
Bit 5
Bit 5
Reserved
Bit 4
DAOSR
Bit 4
Pair
First pair (default)
Second pair
Third pair
Fourth pair
Sampling Rate
f
f
f
f
f
f
f
Reserved
Pair
First pair (default)
Second pair
Third pair
Fourth pair
S
S
S
S
S
S
S
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Bit 3
ADOSR
Bit 3
S
. The base sampling rate is determined by the operating frequency
Bit 2
Bit 2
Base Sampling Rate (f
48 kHz, base (default)
8 kHz
12 kHz
16 kHz
24 kHz
32 kHz
96 kHz
Bit 1
Bit 1
CONVSR[2:0]
S
= 48 kHz)
ADPAIR[1:0]
ADAU1761
Bit 0
Bit 0