AD7983BCPZ-RL Analog Devices Inc, AD7983BCPZ-RL Datasheet - Page 18

• Manufacturer Part Number: AD7983BCPZ-RL
• Description: IC,A/D CONVERTER,SINGLE,16-BIT,LLCC,10PIN
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7983BCPZ-RL

• Number Of Bits: 16
• Sampling Rate (per Second): 1.33M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 12mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-WFDFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7983
CS MODE, 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7983 is connected
to an SPI-compatible digital host that has an interrupt input.
The connection diagram is shown in Figure 28, and the
corresponding timing is given in Figure 29.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time
elapses and then held low for the maximum conversion time to
guarantee the generation of the busy signal indicator. When the
conversion is complete, SDO goes from high impedance to low.
With a pull-up on the SDO line, this transition can be used as an
interrupt signal to initiate the data read back controlled by the
digital host. The AD7983 then enters the acquisition phase and
goes into standby mode. The data bits are then clocked out,
MSB first, by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can be used to capture
the data, a digital host using the SCK falling edge allows a faster
reading rate provided it has an acceptable hold time. After the
optional 17th SCK falling edge or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
ACQUISITION
SDI = 1
CNV
SCK
SDO
CONVERSION
Figure 29. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High)
t
CONV
t
CNVH
1
t
Rev. A | Page 18 of 24
HSDO
D15
t
2
CYC
ACQUISITION
D14
If multiple AD7983s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended that this contention be
kept as short as possible to limit extra power dissipation.
t
3
ACQ
t
DSDO
VIO
t
SCKL
15
t
SCKH
SDI
Figure 28. CS Mode, 3-Wire with Busy Indicator
AD7983
t
SCK
CNV
SCK
16
Connection Diagram (SDI High)
D1
SDO
17
D0
VIO
47kΩ
t
DIS
CONVERT
DATA IN
IRQ
CLK
DIGITAL HOST