AD9268BCPZ-105 Analog Devices Inc, AD9268BCPZ-105 Datasheet - Page 15

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AD9268BCPZ-105

Manufacturer Part Number
AD9268BCPZ-105
Description
Dual 16 Bit 105 High SNR ADC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9268BCPZ-105

Design Resources
Powering AD9268 with ADP2114 for Increased Efficiency (CN0137)
Number Of Bits
16
Sampling Rate (per Second)
105M
Data Interface
Serial, SPI™
Number Of Converters
2
Power Dissipation (max)
590mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9268BCPZ-105
Manufacturer:
ADI
Quantity:
530
Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode)
Pin No.
ADC Power Supplies
10, 19, 28, 37
49, 50, 53, 54, 59,
60, 63, 64
0
ADC Analog
51
52
62
61
55
56
58
57
1
2
Digital Input
3
Digital Outputs
5
4
7
6
9
8
12
Mnemonic
DRVDD
AVDD
AGND,
Exposed Pad
VIN+A
VIN−A
VIN+B
VIN−B
VREF
SENSE
RBIAS
VCM
CLK+
CLK−
SYNC
D0+ (LSB)
D0− (LSB)
D1+
D1−
D2+
D2−
D3+
NOTES
1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE
D0– (LSB)
D0+ (LSB)
PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED
PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
DRVDD
Figure 7. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)
SYNC
CLK+
CLK–
Input
Type
Supply
Supply
Ground
Input
Input
Input
Input
Input/Output
Input
Input/Output
Output
Input
Input
Output
Output
Output
Output
Output
Output
Output
D1–
D1+
D2–
D2+
D3–
D3+
D4–
D4+
D5–
D5+
10
12
13
14
15
16
11
1
2
3
4
5
6
7
8
9
PIN 1
INDICATOR
Description
Digital Output Driver Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
The exposed thermal pad on the bottom of the package provides the analog
ground for the part. This exposed pad must be connected to ground for proper
operation.
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Voltage Reference Input/Output.
Voltage Reference Mode Select. See Table 11 for details.
External Reference Bias Resistor.
Common-Mode Level Bias Output for Analog Inputs.
ADC Clock Input—True.
ADC Clock Input—Complement.
Digital Synchronization Pin. Slave mode only.
Channel A/Channel B LVDS Output Data 0—True.
Channel A/Channel B LVDS Output Data 0—Complement.
Channel A/Channel B LVDS Output Data 1—True.
Channel A/Channel B LVDS Output Data 1—Complement.
Channel A/Channel B LVDS Output Data 2—True.
Channel A/Channel B LVDS Output Data 2—Complement.
Channel A/Channel B LVDS Output Data 3—True.
Rev. A | Page 15 of 44
PARALLEL LVDS
(Not to Scale)
AD9268
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PDWN
OEB
CSB
SCLK/DFS
SDIO/DCS
OR+
OR–
D15+ (MSB)
D15– (MSB)
D14+
D14–
DRVDD
D13+
D13–
D12+
D12–
AD9268

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